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參數(shù)資料
| 型號： | ICS1893BFILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 77/133頁 |
| 文件大?。?/td> | 0K |
| 描述： | PHYCEIVER LOW PWR 3.3V 48-SSOP |
| 標(biāo)準(zhǔn)包裝： | 30 |
| 系列： | PHYceiver™ |
| 類型： | PHY 收發(fā)器 |
| 規(guī)程： | MII |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-BSSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-SSOP |
| 包裝： | 管件 |
| 其它名稱： | 1893BFILF |
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ICS1893BF, Rev. F, 5/13/10
May, 2010
48
Chapter 6 Functional Blocks
ICS1893BF Data Sheet - Release
Copyright 2009, IDT, Inc.
All rights reserved.
Upon receiving a valid STA transaction, during a power-on or hardware reset an ICS1893BF compares the
PHYAD field included within the management frame with the value of its PHYAD bits stored in register 16.
(For information on the PHYAD bits, see Table 7-16.) An ICS1893BF responds to all transactions that
match its stored address bits.
6.6.2.5 Management Frame Register Address
A Management Frame includes a 5-bit register address field, REGAD. This field identifies which of the 32
Management Registers are involved in a transaction between an STA and a PHY.
6.6.2.6 Management Frame Operational Code
A management frame includes a 2-bit operational code field, OP. If the operation code is a:
Read, the REGAD field identifies the register used as the source of data returned to the STA by the
ICS1893BF.
Write, the REGAD identifies the destination register that is to receive the data sent by the STA to the
ICS1893BF.
6.6.2.7 Management Frame Turnaround
A valid management frame includes a turn-around field (TA), which is a 2-bit time space between the
REGAD field and the Data field. This time allows an ICS1893BF and an STA to avoid contentions during
read transactions. During an operation that is a:
Read, an ICS1893BF remains in the high-impedance state during the first bit time and subsequently
drives its MDIO pin to logic zero for the second bit time.
Write, an ICS1893BF waits while the STA transmits a logic one, followed by a logic zero on its MDIO pin.
6.6.2.8 Management Frame Data
A valid management frame includes a 16-bit Data field for exchanging the register contents between the
ICS1893BF and the STA. All Management Registers are 16 bits wide, matching the width of the Data field.
During a transaction that is a:
Read, (OP is 10b) the ICS1893BF obtains the contents of the register identified in the REGAD field and
returns this Data to the STA synchronously with its MDC signal.
Write, (OP is 01b) the ICS1893BF stores the value of the Data field in the register identified in the
REGAD field.
If the STA attempts to:
Read from a non-existent ICS1893BF register, the ICS1893BF returns logic one for all bits in the Data
field, FFFFh.
Write to a non-existent ICS1893BF register, the ICS1893BF isolates the Data field of the management
frame from every reaching the registers.
Note: The first Data bit transmitted and received is the most-significant bit of a Management Register, bit
X.15.
6.6.2.9 Serial Management Interface Idle State
The MDIO signal is in an idle state during the time between STA transactions. When the Serial
Management Interface is in the idle state, the ICS1893BF disables (that is, tri-states) its MDIO pin, which
enters a high-impedance state. The ISO/IEC 8802-3 standard requires that an MDIO signal be idle for at
least one bit time between management transactions. However, the ICS1893BF does not have this
limitation and can support a continual bit stream on its MDIO signals.
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| ICS1893BFILFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BFIT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893BFLF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BFLFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| ICS1893BFT | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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