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參數(shù)資料
| 型號(hào)： | ICS7973DI147 |
| 英文描述： | LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER |
| 中文描述： | 低偏移，1至12個(gè)LVCMOS / LVTTL時(shí)鐘倍頻/零延遲緩沖器 |
| 文件頁(yè)數(shù)： | 10/16頁(yè) |
| 文件大小： | 287K |
| 代理商： | ICS7973DI147 |
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87973DYI-147
www.icst.com/products/hiperclocks.html
10
REV. A AUGUST 26, 2003
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
L
F
C
Qx F
REEZE
Internal
Qx Internal
Qx Out
FRZ_CLK
FRZ_DATA
StBt
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
A
PPLICATION
I
NFORMATION
F
IGURE
2A. F
REEZE
D
ATA
I
NPUT
P
ROTOCOL
U
SING
T
HE
O
UTPUT
F
REEZE
C
IRCUITRY
O
VERVIEW
To enable low power states within a system, each output of
ICS87973I-147 (Except QC0 and QFB) can be individually fro-
zen (stopped in the logic “0” state) using a simple serial inter-
face to a 12 bit shift register. A serial interface was chosen to
eliminate the need for each output to have its own Output En-
able pin, which would dramatically increase pin count and pack-
age cost. Common sources in a system that can be used to
drive the ICS87973I-147 serial interface are FPGA’s and ASICs.
P
ROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which
can be frozen has its own freeze enable bit in the 12 bit shift
register. The sequence is started by supplying a logic “0” start
bit followed by 12NRZ freeze enable bits. The period of each
FRZ_DATA bit equals the period of the FRZ_CLK signal. The
FRZ_DATA serial transmission should be timed so the
ICS87973I-147 can sample each FRZ_DATA bit with the rising
edge of the FRZ_CLK signal. To place an output in the freeze
state, a logic “0” must be written to the respective freeze enable
bit in the shift register. To unfreeze an output, a logic “1” must be
written to the respective freeze enable bit. Outputs will not be-
come enabled/disabled until all 12 data bits are shifted into the
shift register. When all 12 data bits are shifted in the register, the
next rising edge of FRZ_CLK will enable or disable the outputs.
If the bit that is following the 12th bit in the register is a logic “0”,
it is used for the start bit of the next cycle; otherwise, the device
will wait and won’t start the next cycle until it sees a logic “0” bit.
Freezing and unfreezing of the output clock is synchronous (see
the timing diagram below). When going into a frozen state, the
output clock will go LOW at the time it would normally go LOW,
and the freeze logic will keep the output low until unfrozen. Like-
wise, when coming out of the frozen state, the output will go
HIGH only when it would normally go HIGH. This logic, there-
fore, prevents runt pulses when going into and out of the frozen
state.
F
IGURE
2B. O
UTPUT
D
ISABLE
T
IMING
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