參數(shù)資料
型號: ICS7973DI147
英文描述: LOW SKEW, 1-TO-12 LVCMOS / LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
中文描述: 低偏移,1至12個LVCMOS / LVTTL時鐘倍頻/零延遲緩沖器
文件頁數(shù): 9/16頁
文件大?。?/td> 287K
代理商: ICS7973DI147
87973DYI-147
www.icst.com/products/hiperclocks.html
9
REV. A AUGUST 26, 2003
Integrated
Circuit
Systems, Inc.
ICS87973I-147
L
OW
S
KEW
, 1-
TO
-12
LVCMOS / LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V±5%
-1.65V±5%
C
YCLE
-
TO
-C
YCLE
J
ITTER
O
UTPUT
S
KEW
tsk(o)
V
DDO
2
V
DDO
2
Qy
Qx
S
TATIC
P
HASE
O
FFSET
(D
IFFERENTIAL
)
nCLK
EXT_FB
CLK
t()
V
DD
2
(where t() is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t()
mean
= Static Phase Offset
V
CMR
Cross Points
V
PP
nCLK
CLK
GND
V
DD
S
TATIC
P
HASE
O
FFSET
(LVCMOS)
t()
V
DD
2
V
DD
2
(where t() is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t()
mean
= Static Phase Offset
CLK0,
CLK1
EXT_FB
V
DD
,
V
DDA
, V
DDO
GND
D
IFFERENTIAL
I
NPUT
L
EVEL
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
V
DDO
2
V
DDO
2
V
DDO
2
t
cycle n
t
cycle n+1
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
Clock
Outputs
0.8V
2V
2V
0.8V
t
R
t
F
O
UTPUT
R
ISE
/F
ALL
T
IME
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
QA0:QA3,
QB0:QB3,
QC0:QC3,
QSYNC,
QFB
O
UTPUT
D
UTY
C
YCLE
/ P
ULSE
W
IDTH
P
ERIOD
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