FEMTOCLOCK
參數資料
型號: ICS841664AGILF
廠商: IDT, Integrated Device Technology Inc
文件頁數: 2/19頁
文件大?。?/td> 0K
描述: IC CLOCK GENERATOR 28-TSSOP
標準包裝: 48
系列: HiPerClockS™, FemtoClock™
類型: 時鐘發(fā)生器,扇出配送,多路復用器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: HCSL,LVCMOS,LVTTL
電路數: 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 無/是
頻率 - 最大: 156.25MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.240",6.10mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 管件
其它名稱: 800-2386-5
841664AGILF
ICS841664AGILF-ND
ICS841664AGI REVISION A JULY 15, 2013
10
2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet
FEMTOCLOCK CRYSTAL-TO-HCSL CLOCK GENERATOR
Parameter Measurement Information, continued
SE Measurement Points For Absolute Cross Point/Swing
Applications Information
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k
resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1k
resistor can be tied from the REF_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullups and pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k
resistor can be used.
Outputs:
HCSL Outputs
All unused HCSL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
LVCMOS Outputs
The unused LVCMOS output can be left floating. There should be no
trace attached.
= -0.30V
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