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參數(shù)資料
| 型號： | ICS841664AGILF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GENERATOR 28-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 時鐘發(fā)生器，扇出配送，多路復(fù)用器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 156.25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 其它名稱： | 800-2386-5 841664AGILF ICS841664AGILF-ND |
ICS841664AGI REVISION A JULY 15, 2013
12
2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet
FEMTOCLOCK CRYSTAL-TO-HCSL CLOCK GENERATOR
Overdriving the XTAL Interface
The XTAL_IN input can be overdriven by an LVCMOS driver or by one
side of a differential driver through an AC coupling capacitor. The
XTAL_OUT pin can be left floating. The amplitude of the input signal
should be between 500mV and 1.8V and the slew rate should not be
less than 0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be
reduced from full swing to at least half the swing in order to prevent
signal interference with the power rail and to reduce internal noise.
Figure 2A shows an example of the interface diagram for a high
speed 3.3V LVCMOS driver. This configuration requires that the sum
of the output impedance of the driver (Ro) and the series resistance
(Rs) equals the transmission line impedance. In addition, matched
termination at the crystal input will attenuate the signal in half. This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50
applications,
R1 and R2 can be 100
. This can also be accomplished by removing
R1 and changing R2 to 50
. The values of the resistors can be
increased to reduce the loading for a slower and weaker LVCMOS
driver. Figure 2B shows an example of the interface diagram for an
LVPECL driver. This is a standard LVPECL termination with one side
of the driver feeding the XTAL_IN input. It is recommended that all
components in the schematics be placed in the layout. Though some
components might not be used, they can be utilized for debugging
purposes. The datasheet specifications are characterized and
guaranteed by using a quartz crystal as the input.
Figure 2A. General Diagram for LVCMOS Driver to XTAL Input Interface
Figure 2B. General Diagram for LVPECL Driver to XTAL Input Interface
VCC
XTAL_OUT
XTAL_IN
R1
100
R2
100
Zo = 50 ohms
Rs
Ro
Zo = Ro + Rs
C1
.1uf
LVCMOS Driver
XTAL_OUT
XTAL_IN
Zo = 50 ohms
C2
.1uf
LVPECL Driver
Zo = 50 ohms
R1
50
R2
50
R3
50
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| ICS841664AGILFT | 功能描述:IC CLOCK GENERATOR 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS841664I | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCK? CRYSTAL-TO-HCSL CLOCK GENERATOR |
| ICS841N254AKILF | 功能描述:IC CLK SYNTH PLL 250MHZ 32VFQFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:FemtoClock® NG 標(biāo)準(zhǔn)包裝:27 系列:Precision Edge® 類型:頻率合成器 PLL:是 輸入:PECL，晶體 輸出:PECL 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/是 頻率 - 最大:800MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 5.25 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC 包裝:管件 |
| ICS841N254AKILFT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK SYNTHESIZER 32VFQFN |
| ICS841N254I | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCK? NG Crystal-to-LVDS/HCSL Clock Synthesizer |
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