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參數(shù)資料
| 型號： | ICS842023BGLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN ETHERNET 25MHZ 8TSSOP |
| 標準包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng) |
| 輸入： | 晶體 |
| 輸出： | HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 340MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 8-TSSOP |
| 包裝： | 帶卷 (TR) |
ICS842023
FEMTOCLOCKCRYSTAL-TO-HSTL CLOCK GENERATOR
IDT / ICS HSTL CLOCK GENERATOR
8
ICS842023BG REV. A NOVEMBER 2, 2012
Application Information
Crystal Input Interface
The ICS842023 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error.
The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
Figure 1. Crystal Input Interface
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform-
ance, power supply isolation is required. The ICS842023 provides
separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD and VDDA should be
individually connected to the power supply plane through vias, and
0.01F bypass capacitors should be used for each pin. Figure 3
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10
resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
Figure 3. Power Supply Filtering
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
22pF
C2
22pF
VDD
VDDA
3.3V or 2.5V
10
Ω
10F
.01F
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