參數(shù)資料
型號(hào): ICS842023BGLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/15頁
文件大?。?/td> 0K
描述: IC CLK GEN ETHERNET 25MHZ 8TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™, FemtoClock™
類型: 時(shí)鐘/頻率發(fā)生器
PLL:
主要目的: 以太網(wǎng)
輸入: 晶體
輸出: HSTL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 340MHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-TSSOP
包裝: 帶卷 (TR)
ICS842023
FEMTOCLOCKCRYSTAL-TO-HSTL CLOCK GENERATOR
IDT / ICS HSTL CLOCK GENERATOR
9
ICS842023BG REV. A NOVEMBER 2, 2012
Termination for HSTL Outputs
Figure 4. HSTL Output Termination
Schematic Example
Figure 5 shows an example of the ICS842023 application
schematic. In this example, the device is operated at VDD = 3.3V.
The 18pF parallel resonant 25MHz crystal is used. The C1 = 22pF
and C2 = 22pF are recommended for frequency accuracy. For
different board layouts, the C1 and C2 may be slightly adjusted for
optimizing frequency accuracy. An example of HSTL termination is
shown in this schematic.
Note: Thermal pad (E-pad) must be connected to ground (GND).
Figure 5. ICS842023 Schematic Example
VDDO
Zo = 50
HSTL
+
-
ICS HiPerClockS
VDD
R2
50
R1
50
Zo = 50
HSTL
HSTL Driv er
RD2
1K
OE
R2
50
R3
50
RU1
1K
VDD=3.3V
U1
ICS842023
1
2
3
4
8
7
6
5
VDDA
GND
XTAL_OUT
XTAL_IN
VDD
Q
nQ
OE
C1
22pF
VDD
+
-
Logic Control Input Examples
1 8 p F
VDDA
C4
0.1u
VDD
To Logic
Input
pins
C3
0.1uF
Set Logic
Input to
'1'
R1
10
X1
25MHz
To Logic
Input
pins
Zo = 50 Ohm
VDD
Zo = 50 Ohm
C2
22pF
C5
10u
RD1
Not Install
VDD
RU2
Not Install
Set Logic
Input to
'0'
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