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參數(shù)資料
| 型號(hào)： | ICS842023BGLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GEN ETHERNET 25MHZ 8TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 時(shí)鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng) |
| 輸入： | 晶體 |
| 輸出： | HSTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無(wú)/是 |
| 頻率 - 最大： | 340MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-TSSOP |
| 包裝： | 帶卷 (TR) |
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ICS842023
FEMTOCLOCKCRYSTAL-TO-HSTL CLOCK GENERATOR
IDT / ICS HSTL CLOCK GENERATOR
10
ICS842023BG REV. A NOVEMBER 2, 2012
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS842023.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS842023 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (84mA + 11mA) = 329.18mW
Power (outputs)MAX = 94.32mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 329.18mW + 94.32mW = 423.49mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj =
JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 129.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.423W * 129.5°C/W = 124.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (multi-layer).
Table 7. Thermal Resistance JA for 8 Lead TSSOP, Forced Convection
JA vs. Air Flow
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
129.5°C/W
125.5°C/W
123.5°C/W
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