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參數(shù)資料
| 型號： | ICS843002CY-31LFT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 13/27頁 |
| 文件大小： | 463K |
| 代理商： | ICS843002CY-31LFT |
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 7, 2005
20
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED
FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
PRELIMINARY
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843002-31 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC, VCCA, VCCA_XO,
and V
CCO_X should be individually connected to the power sup-
ply plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10
Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
CCA pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 3. POWER SUPPLY FILTERING
10
Ω
V
CCA
10
μF
.01
μF
3.3V
.01
μF
V
CC
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK0 /nCLK0 accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both V
SWING and VOH must
meet the V
PP and VCMR input requirements. Figures 4A to 4D
show interface examples for the HiPerClockS CLK0/nCLK0
input driven by the most common driver types. The input inter-
faces suggested here are examples only. Please consult with
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
the vendor of the driver component to confirm the driver termi-
nation requirements. For example in Figure 4A, the input ter-
mination applies for ICS HiPerClockS LVHSTL drivers. If you
are using an LVHSTL driver from another vendor, use their
termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS843002CY-31T | 700 MHz, OTHER CLOCK GENERATOR, PQFP64 |
| ICS843003AGLF | 700 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AG-01LFT | 156.25 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AG-02LFT | 637.5 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| ICS843004AG-02LF | 680 MHz, OTHER CLOCK GENERATOR, PDSO24 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843002CY-31T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| ICS843002I | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002I-01 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002I-40 | 制造商:ICS 制造商全稱:ICS 功能描述:175MHZ, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| ICS843002I-41 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
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