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參數(shù)資料
| 型號： | ICS843002CY-31LFT |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PQFP64 |
| 封裝： | 10 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 14/27頁 |
| 文件大小： | 463K |
| 代理商： | ICS843002CY-31LFT |
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843002CY-31
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 7, 2005
21
Integrated
Circuit
Systems, Inc.
ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED
FREQUENCY TRANSLATOR AND JITTER ATTENUATOR
PRELIMINARY
FIGURE 5. SINGLE-ENDED CLOCK INPUT INTERFACE
3.3V
CLK
nCLK
3.3V
51k
(no connection)
Differential
Input Stage
LVTTL
or LVCMOS
Logic Output
Series
Termination
Optional
Series
Filter
Resistor
nCLK0
CLK0
Internal Device Circuitry
External Circuitry
DIFFERENTIAL CLOCK INPUT CIRCUIT
USING THE DIFFERENTIAL INTERFACE FOR SINGLE-ENDED CLOCKS
The differential interface (CLK0/nCLK0) can be used as a
third single-ended input to support an LVCMOS or LVTTL
clock driver. The clock input is connected to the CLK0 input
pin, and the nCLK0 pin is left unconnected. To help reduce
interference with the internal VCO circuits, an external
resistor can be placed in series with the clock signal near
the CLK0 input pint. Combined with the input pin capaci-
tance, this resistor acts as a low pass signal filter. The
typical value of this optional series filter resistor is 100
Ω.
This will lower both the amplitude and edge rate of the
clock input signal. In the case of a very short clock trace a
series termination register may not be needed.
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
Ω resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
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| ICS843004AG-02LFT | 637.5 MHz, OTHER CLOCK GENERATOR, PDSO24 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS843002CY-31T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ FEMTOCLOCKS⑩ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR |
| ICS843002I | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO-3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002I-01 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS-TM CRYSTAL-TO- 3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER |
| ICS843002I-40 | 制造商:ICS 制造商全稱:ICS 功能描述:175MHZ, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
| ICS843002I-41 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR |
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