8732AY-01
www.idt.com
REV. E MAY 2, 2013
9
ICS8732-01
LOW VOLTAGE, LOW SKEW
3.3V LVPECL CLOCK GENERATOR
FIGURE 4C. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING and VOH must meet the
V
PP and VCMR input requirements.
Figures 4A to 4D show
interface examples for the CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
FIGURE 4A. CLK/NCLK INPUT DRIVEN BY
LVHSTL DRIVER
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8732-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC, VCCA and VCCO
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for
each pin. To achieve optimum jitter performance, power
supply isolation is required.
Figure 3 illustrates how a 10
Ω
resistor along with a 10
μF and a .01μF bypass capacitor
should be connected to each V
CCA pin.
FIGURE 3. POWER SUPPLY FILTERING
10
Ω
V
CCA
10
μF
.01
μF
3.3V
.01
μF
V
CC
POWER SUPPLY FILTERING TECHNIQUES
component to confirm the driver termination requirements. For
example in
Figure 4A, the input termination applies for LVHSTL
drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.