參數(shù)資料
型號: ICS874002AGLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/15頁
文件大?。?/td> 0K
描述: IC JITTER ATTENUATOR 20-TSSOP
產(chǎn)品培訓模塊: PCI-Express
標準包裝: 74
系列: HiPerClockS™, PCI Express® (PCIe)
類型: 扇出緩沖器(分配),漂移衰減器
PLL:
主要目的: PCI Express(PCIe)
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 160MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 1250 (CN2011-ZH PDF)
其它名稱: 800-1213
800-1213-5
800-1213-ND
874002AGLF
PCI EXPRESS/JITTER ATTENUATOR
ICS874002
IDT / ICS PCI EXPRESS/JITTER ATTENUATOR
1
ICS874002AG REV. A DECEMBER 6, 2006
GENERAL DESCRIPTION
The ICS874002 is a high performance Differential-
to-LVDS Jitter Attenuator designed for use in PCI
Express systems. In some PCI Express systems,
such as those found in desktop PCs, the PCI
Express clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a jitter attenuator may be required to attenuate
high frequency random and deterministic jitter components
from the PLL synthesizer and from the system board. The
ICS874002 has 3 PLL bandwidth modes: 200kHz, 400kHz, and
800kHz. The 200kHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may
be attenuated. The 400kHz provides an intermediate band-
width that can easily track triangular spread profiles, while
providing good jitter attenuation. The 800kHz bandwidth
provides the best tracking skew and will pass most spread
profiles, but the jitter attenuation will not be as good as the
lower bandwidth modes. Because some 2.5Gb serdes have x20
multipliers while others have than x25 multipliers, the
ICS874002 can be set for 1:1 mode or 5/4 multiplication mode
(i.e. 100MHz input/125MHz output) using the F_SEL pin.
The ICS874002 uses IDT’s 3rd Generation FemtoClockTM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 20 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
FEATURES
Two differential LVDS output pair
One differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 160MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
3.3V operating supply
Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS
ICS
BLOCK DIAGRAM
BW_SEL
0 = PLL Bandwidth: 200kHz
Float = PLL Bandwidth: 400kHz (Default)
1 = PLL Bandwidth: 800kHz
PLL BANDWIDTH (TYPICAL)
÷5 (fixed)
VCO
490 - 640 MHz
Phase
Detector
Output Divider
0 ÷5 (default)
1 ÷4
QA0
nQA0
QA1
nQA1
FB_OUT
nFB_OUT
BW_SEL
0 = 200kHz
Float = 400kHz
1 = 800kHz
CLK
nCLK
FB_IN
nFB_IN
F_SEL
MR
OE
Float
Pulldown
Pullup
Pulldown
Pullup
Pulldown
PIN ASSIGNMENT
ICS874002
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
nQA0
VDDO
FB_OUT
nFB_OUT
MR
BW_SEL
nc
VDDA
F_SEL
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QA0
VDDO
QA1
nQA1
nFB_IN
FB_IN
GND
nCLK
CLK
OE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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