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參數(shù)資料
| 型號： | ICS9214YGLF-T |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9214 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 0.173 INCH, 0.65 MM PITCH, LEAD FREE, MO-153, TSSOP-28 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 228K |
| 代理商： | ICS9214YGLF-T |
10
Integrated
Circuit
Systems, Inc.
ICS9214
0809E—11/17/06
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
θ
JA
Still air
120
°C/W
θ
JA
1 m/s air flow
95
°C/W
θ
JA
3 m/s air flow
80
°C/W
Thermal Resistance Junction to Case
θ
JC
20
°C/W
Thermal Resistance Junction to Top of
Case
Ψ
JT
Still Air
4.5
°C/W
Maximum Case Temp
120
°C
Thermal Resistance Junction to
Ambient
AC Characteristics-Outputs
TA = 0°C to +70°C; Supply Voltage AVDD2.5, VDD2.5 = 2.5 V +/- 0.125V (unless otherwise stated)
PARAMETER
1
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Output clock cycle time
tCYCLE
1.5
2.5
ns
f = 400 to 635 MHz
-
40
ps
f = 635 to 800 MHz
-
30
ps
Output Phase error when
tracking SSC
tERR,SSC
-100
100
ps
Change in skew
tSKEW
3
TA = 0°C to +70°C,
AVDD2.5, VDD2.5 =
2.5 V +/- 0.125V
-15
ps
Long term average output
duty cycle
DC
45
55
%
f = 400 to 635 MHz
-
40
ps
f = 635 to 800 MHz
-
30
ps
Output rise and fall times
tR, tF
20% to 80% of output
voltage
100
300
ps
Difference between
output rise and fall time
on same pin of a single
device
tR-F
20% to 80% of output
voltage, f = 400 to 800 MHz
-
100
ps
Dynamic output
impedance
ZOUT
4
VOL = 0.9 V
1000
-
Notes:
5. Guaranteed by design and characterization, not 100% tested in production
is measured at common mode voltage.
2. Output short-term jitter is the absolute value fo the worst case deviation and is
defined in the Jitter section.
3. tSKEW is the timing difference between any two of the four differential clocks and
4. Zout is defined at the output pins.
1. Max and min output clock cycle times are based on nominal output frequencies
of 400 and 667 MHz respectively. For spread spectrum modulated input clocks,
the output clocks track the input modulation.
Short term jitter (over 1 to
6 clock cycles)
tJ
2
tDCERR
Cycle-to-cycle duty cycle
error
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