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參數(shù)資料
| 型號(hào)： | ICS9248YF-96-T |
| 英文描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 中文描述： | 頻率發(fā)生器 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大?。?/td> | 206K |
| 代理商： | ICS9248YF-96-T |
5
ICS9248-96
0311D—04/23/04
Byte 1: Control Register
(1= enable, 0 = disable)
T
I
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
#
N
-
-
-
8
2
7
2
6
2
-
3
I
P
D
W
X
X
X
X
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
D
7
6
5
4
3
2
1
0
#
#
#
4
3
0
2
_
M
M
v
R
R
D
S
S
S
S
4
8
8
F
F
F
2
4
4
(
z
H
M
4
2
=
0
,
1
0
)
e
_
M
H
_
_
M
z
z
8
H
H
1
F
A
Byte 4: Control Register
(1= enable, 0 = disable)
T
I
B
N
I
P
7
t
B
-
6
t
B
8
5
t
B
7
4
t
B
-
3
t
B
7
4
2
t
B
-
1
t
B
4
4
0
t
B
5
4
#
D
W
1
1
1
X
1
X
1
1
P
N
O
I
T
P
I
R
C
S
E
)
e
1
0
O
I
Q
C
I
P
#
L
C
U
L
C
U
D
v
R
6
6
V
3
6
V
3
E
R
F
A
O
I
1
S
F
P
C
P
C
(
_
_
6
#
C
I
P
A
1
0
K
K
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
T
I
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
t
B
#
N
0
2
1
1
1
1
1
1
1
I
P
D
W
1
1
1
1
1
1
1
1
P
N
O
I
T
P
I
R
C
S
E
7
6
5
4
3
2
1
0
D
K
L
K
L
K
L
K
L
K
L
K
L
K
L
K
L
7
6
5
4
3
2
1
0
C
C
C
C
C
C
C
C
I
I
I
I
I
I
I
I
C
C
C
C
C
C
C
C
P
P
P
P
P
P
P
P
9
7
6
5
3
2
1
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
P
7
t
B
2
3
6
t
B
3
3
5
t
B
5
3
4
t
B
6
3
3
t
B
7
3
2
t
B
9
3
1
t
B
0
4
0
t
B
1
4
D
W
1
1
1
1
1
1
1
1
N
O
I
T
P
I
R
C
S
E
7
6
5
4
3
2
1
0
D
M
M
M
M
M
M
M
M
A
A
A
A
A
A
A
A
R
R
R
R
R
R
R
R
D
D
D
D
D
D
D
D
S
S
S
S
S
S
S
S
Notes:
1. Disable means outputs are held LOW and are
disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted
logic load of the input frequency select pin conditions.
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
7
B
-
1
6
B
-
1
5
B
-
1
4
B
-
1
3
B
-
1
2
B
-
1
1
B
-
1
0
B
-
1
N
O
I
T
P
I
R
C
S
E
d
d
d
d
d
d
d
d
D
e
e
e
e
e
e
e
e
v
R
v
R
v
R
v
R
v
R
v
R
v
R
v
R
T
I
B
B
B
B
B
B
B
B
B
#
N
-
-
-
-
-
-
-
-
I
P
D
W
0
0
0
0
0
1
1
0
P
N
O
I
T
P
I
R
C
N
N
N
N
N
N
N
N
S
(
(
(
(
(
(
(
(
E
d
d
d
d
d
d
d
d
D
e
e
e
e
e
e
e
e
7
6
5
4
3
2
1
0
)
)
)
)
)
)
)
)
v
R
v
R
v
R
v
R
v
R
v
R
v
R
v
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register. Writing into this
register can cause malfunction
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