- 您現(xiàn)在的位置：買賣IC網 > PDF目錄360784 > ICS9248YF-96LF-T Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ PDF資料下載
參數(shù)資料
| 型號： | ICS9248YF-96LF-T |
| 英文描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 中文描述： | 頻率發(fā)生器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 206K |
| 代理商： | ICS9248YF-96LF-T |
7
ICS9248-96
0311D—04/23/04
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low, all clocks need to be
driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than
3 ms. The power down latency should be as short as possible but conforming to the sequence requirements shown
below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state
of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock
cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS9248YF-96-T | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS932S202 | Frequency Timing Generator for Differential PIIIType Dual-CPU Systems |
| ICS932S208 | Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
| ICS932S208YFLF-T | Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
| ICS932S208YGLF-T | Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248YF-96-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-97-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for PENTIUM II Systems |
| ICS9248YF-98-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YF-99 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248YG-101-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6 |
發(fā)布緊急采購，3分鐘左右您將得到回復。