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參數(shù)資料
| 型號： | ICS9341yF |
| 英文描述： | 133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| 中文描述： | 133MHz的時鐘發(fā)生器和集成緩沖器，用于PowerPC的⑩ |
| 文件頁數(shù)： | 9/9頁 |
| 文件大?。?/td> | 207K |
| 代理商： | ICS9341YF |
ICS9341
SSOP Package
SYMBOL
COMMON DIMENSIONS
MIN.
NOM.
.095
.101
.008
.012
.088
.090
.008
.010
.005
-
See Variations
.292
.296
0.025 BSC
.400
.406
.010
.013
.024
.032
See Variations
0
°
5
°
.085
.093
VARIATIONS
D
N
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
NOM.
.625
MAX.
.630
A
A1
A2
B
C
D
E
e
H
h
L
N
AC
48
.299
.410
.016
.040
μ
X
8
°
.100
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Ordering Information
ICS9341
y
F
*+,
#>>-(
!"
#
17<
ICS XXXX
y
F - PPP
相關PDF資料 |
PDF描述 |
|---|---|
| ICS9342yF-T | 133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS9342 | 133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | DDR Phase Lock Loop Clock Driver |
| ICS93705 | DDR Phase Lock Loop Zero Delay Clock Buffer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9342 | 制造商:ICS 制造商全稱:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS9342AFLF | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9342YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
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