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參數(shù)資料
| 型號(hào)： | ICS93716YF-T |
| 英文描述： | Low Cost DDR Phase Lock Loop Clock Driver |
| 中文描述： | 低成本的DDR鎖相環(huán)時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 89K |
| 代理商： | ICS93716YF-T |
6
ICS93716
0420E—04/01/03
Notes:
1.
2.
Refers to transition on noninverting output in PLL bypass mode.
While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, were
the cycle (t
c
) decreases as the frequency goes up.
Switching characteristics guaranteed for application frequency range.
Static phase offset shifted by design.
3.
4.
Timing Requirements
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120
, C
L
=15pF (unless otherwise
PARAMETER
SYMBOL
Max clock frequency
3
freq
op
Application Frequency
Range
3
Input clock duty cycle
d
tin
CONDITIONS
MIN
33
MAX
233
UNITS
MHz
freq
App
60
170
MHz
40
60
%
CLK stabilization
T
STAB
100
μs
Switching Characteristics
T
A
= 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, R
L
= 120
, C
L
=15pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
Low-to high level
propagation delay time
High-to low level propagation
delay time
Duty Cycle
DC
Input clock slew rate
t
sl(I)
Cycle to Cycle Jitter
1
t
cyc
-t
cyc
66/100/125/133/167MHz
Phase error
t
(phase error)4
Output to Output Skew
t
skew
Rise Time, Fall Time
t
r
, t
f
See figure 8
MIN
TYP
MAX
UNITS
t
PLH1
CLK_IN to any output
5.5
ns
t
PHL1
CLK_IN to any output
5.5
ns
49
1
51
4
75
50
100
950
%
v/ns
ps
ps
ps
ps
-150
0
75
650
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