參數(shù)資料
型號: ICS952623YGT
英文描述: Programmable Timing Control Hub for Next Gen P4 processor
中文描述: 可編程定時控制中心,為下一代P4處理器
文件頁數(shù): 13/27頁
文件大?。?/td> 329K
代理商: ICS952623YGT
13
Integrated
Circuit
Systems, Inc.
ICS952623
Advance Information
0758—02/08/05
I
2
C Table: Output Control and Fix Frequency Register
Pin #
1,2,7,8,9,12,13,14,
15,18,19,20,22,23,2
6,27,29,31,32,37,38
,40,41,43,44,46,47
Name
Control Function
Type
0
1
PWD
Bit 7
Test Clock Mode
Test Clock Mode
-
Disable
Enable
0
Bit 6
RESERVED
-
-
-
-
0
Bit 5
RESERVED
FS_A and FS_B
Operation
SRC Frequency
Select
Down/Center
-
Normal
Test Mode
0
Bit 4
RESERVED
-
100MHz
200MHz
0
Bit 3
Spread Type
-
Down
Center
0
Bit 2
Spread Spectrum Mode
Spread
OFF
Spread
ON
0
Bit 1
Bit 0
REF1
REF0
Output Control
Output Control
RW
RW
Disable
Disable
Enable
Enable
1
1
I
2
C Table: Vendor & Revision ID Register
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Type
R
R
R
R
R
R
R
R
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
0
0
1
I
2
C Table: Byte Count Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
1
0
0
0
-
40,41,43,44,46,47
Byte 6
2
1
37,38
7,8,9,12,13,14,15,1
8,19,20,22,23,26,27
,29,31,32,37,38,40,
41,43,44,46,47
Byte 7
-
-
-
-
-
-
-
REVISION ID
VENDOR ID
Byte 8
-
-
-
-
-
-
-
-
Writing to this register
will configure how
many bytes will be
read back, default is
08
= 8 bytes.
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