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參數(shù)資料
| 型號(hào)： | ICSSSTUB32871A |
| 英文描述： | 27-Bit Registered Buffer for DDR2 |
| 中文描述： | 27位注冊(cè)緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 213K |
| 代理商： | ICSSSTUB32871A |
9
1186G—04/16/07
ICSSSTUB32871A
Register Timing
Figure 6 — RESET
CK
(1)
DCSn
RESET
tINACT
tRPHL
RESET to Q
PARIN
(1)
tRPLH
RESET to PTYERR
PTYERR
H, L, or X
H or L
CK
(1)
Dn
(1)
Qn
switches from H to L
(1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic
levels (not floating) for a minimum time of t (max)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICSSSTUB32871AzLFT | 27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32871AzT | 27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32872A | 28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866Az(LF)T | 25-Bit Configurable Registered Buffer for DDR2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICSSSTUB32871AZLFT | 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32871AZT | 制造商:ICS 制造商全稱:ICS 功能描述:27-Bit Registered Buffer for DDR2 |
| ICSSSTUB32872A | 制造商:ICS 制造商全稱:ICS 功能描述:28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866AZ(LF)T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
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