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參數(shù)資料
| 型號(hào)： | ICSSSTUB32871AzT |
| 英文描述： | 27-Bit Registered Buffer for DDR2 |
| 中文描述： | 27位注冊(cè)緩沖DDR2內(nèi)存 |
| 文件頁(yè)數(shù)： | 16/18頁(yè) |
| 文件大小： | 213K |
| 代理商： | ICSSSTUB32871AZT |
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16
1186G—04/16/07
ICSSSTUB32871A
3 Test circuits and switching waveforms (cont’d)
3.4 Partial-parity-out load circuit and voltage measurement information (V
DD
= 1.8 V ± 0.1 V)
All input pulses are supplied by generators having the following characteristics: PRR
Z
o
= 50
; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
10 MHz;
(1) C
L
includes probe and jig capacitance.
Figure 32 — Partial-parity-out load circuit,
V
TT
= V
DD
/2
t
PLH
and t
PHL
are the same as t
PD
.
V
I(PP)
= 600 mV
Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
V
TT
= V
DD
/2
t
PLH
and t
PHL
are the same as t
PD
.
V
IH
= V
REF
+ 250 mV (AC voltage levels) for differential inputs. V
IH
= V
DD
for LVCMOS inputs.
V
IL
= V
REF
- 250 mV (AC voltage levels) for differential inputs. V
IL
= V
DD
for LVCMOS inputs.
Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
VOH
VOL
OUTPUT
tPLH
002aaa375
VTT
VICR
VICR
tPHL
CK
CK
Vi(p-p)
tPHL
002aaa376
LVCMOS RST
INPUT
OUTPUT
VTT
VDD/2
VIH
VIL
VOH
VOL
DUT
Out
Test Point
RL=
CL =
5 pF
(see Note A)
1 k
Ω
Ω
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| ICSSSTUB32872A | 28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866Az(LF)T | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864A | 25-Bit Configurable Registered Buffer for DDR2 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICSSSTUB32872A | 制造商:ICS 制造商全稱:ICS 功能描述:28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866AZ(LF)T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864A | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864AYHLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
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