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參數(shù)資料
| 型號： | ICSSSTUB32871AzT |
| 英文描述： | 27-Bit Registered Buffer for DDR2 |
| 中文描述： | 27位注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 7/18頁 |
| 文件大?。?/td> | 213K |
| 代理商： | ICSSSTUB32871AZT |
7
1186G—04/16/07
ICSSSTUB32871A
Register Timing
CK
Dn
(1)
Qn
tsu
CK
n
n + 1
n + 2
n + 3
n + 4
DCSn
RESET
tACT
th
tPDM, tPDMSS
CK to Q
PARIN
tsu
th
tPHL, tPLH
CK to PTYERR
tPHL
CK to PTYERR
PTYERR
H, L, or X
H or L
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a
minimum time of t (max) to avoid false error.
Figure 4 —
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICSSSTUB32872A | 28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866Az(LF)T | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864A | 25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864AYHLF-T | 25-Bit Configurable Registered Buffer for DDR2 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICSSSTUB32872A | 制造商:ICS 制造商全稱:ICS 功能描述:28-Bit Registered Buffer for DDR2 |
| ICSSSTUBF32866A | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUBF32866AZ(LF)T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864A | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUF32864AYHLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2 |
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