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參數(shù)資料
| 型號： | IDT54FCT388915T70PY |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, 0.65 MM PITCH, SSOP-28 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 145K |
| 代理商： | IDT54FCT388915T70PY |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
10
ENABLE AND DISABLE TEST CIRCUIT
TEST CIRCUITS AND WAVEFORMS
50
TO V
CC
/2, CL = 20PF
PROPAGATION DELAY, OUTPUT SKEW
t
SYNC INPUT
t
"Q" OUTPUTS
t
t
t
t
t
PD
SYNC INPUT
(SYNC (1) or
SYNC (0))
FEEDBACK
INPUT
Q/2 OUTPUT
t
SKEWALL
Q0-Q4
OUTPUTS
Q5 OUTPUT
2Q OUTPUT
SKEWf
SKEWr
SKEWf
SKEWr
CYCLE
CYCLE
1.5V
V
CC/2
V
CC/2
V
CC/2
1.5V
V
CC/2
(These waveforms represent the configuration of Figure 3a)
NOTES:
1. The FCT388915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does not require a 50% duty cycle.
2. All skew specs are measured between the V
CC
/2 crossing point of the appropriate output edges. All skews are specified as "windows", not as
±
deviation
around a center point.
3. If a Q ouput is connected to the FEEDBACK input (this situation is not shown), the Q output frequency would match the SYNC input frequency, the 2Q
output would run at twice the SYNC frequency and the Q/2 output would run at half the SYNC frequency.
ENABLE AND DISABLE TIMES
CONTROL
INPUT
3V
1.5V
0V
3V
0V
3052 drw 07
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
6V
SWITCH
GND
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
3052 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
2. Pulse Generator for All Pulses: t
F
≤
2.5ns; t
R
≤
2.5ns
SWITCH POSITION
Test
Switch
6V
Disable Low
Enable Low
Disable High
Enable High
GND
3052 tbl 10
DEFINITIONS:
C
L
=
Load capacitance: includes jig and probe capacitance.
R
T
=
Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
Pulse
Generator
D.U.T.
V
CC
V
IN
V
OUT
100
100
R
T
V
CC
20pF
C
L
3052 drw 05
Pulse
Generator
D.U.T.
V
CC
V
IN
V
OUT
500
GND
6.0V
500
R
T
3052 drw 06
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PDF描述 |
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| IDT74FCT388915T70PY | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T70PYB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
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