- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377480 > IDT54FCT388915T70PY (INTEGRATED DEVICE TECHNOLOGY INC) 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) PDF資料下載
參數(shù)資料
| 型號： | IDT54FCT388915T70PY |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| 中文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 5.30 MM, 0.65 MM PITCH, SSOP-28 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 145K |
| 代理商： | IDT54FCT388915T70PY |
IDT54/74FCT388915T 70/100/133/150
3.3V LOW SKEW PLL-BASED CLOCK DRIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
9.8
9
CMMU
CMMU
CPU
CMMU
CMMU
CMMU
CMMU
CMMU
CPU
CMMU
CMMU
CMMU
PLL
2f
PLL
2f
CPU
CARD
CPU
CARD
CLOCK
@f
SYSTEM
CLOCK
SOURCE
FCT388915T
FCT388915T
DISTRIBUTE
CLOCK @f
CLOCK @2f
at point of use
MEMORY
CONTROL
PLL
2f
MEMORY
CARDS
CLOCK @2f
at point of use
FCT388915T
Figure 4. Multiprocessing Application Using the FCT388915T for Frequency Multiplication
and Low Board-to-Board skew
FCT388915T System Level Testing Functionality
When the PLL_EN pin is LOW, the PLL is bypassed and the
FCT388915T is in low frequency "test mode". In test mode
(with FREQ_SEL HIGH), the 2Q output is inverted from the
selected SYNC input, and the Q outputs are divide-by-2
(negative edge triggered) of the SYNC input, and the Q/2
output is divide-by-4 (negative edge triggered). With
FREQ_SEL LOW the 2Q output is divide-by-2 of the SYNC,
the Q outputs divide-by-4, and the Q/2 output divide-by-8.
These relationships can be seen in the block diagram. A
recommended test configuration would be to use SYNC0 or
SYNC1 as the test clock input, and tie PLL_EN and REF_SEL
together and connect them to the test select logic.
This functionality is needed since most board-level testers
run at 1 MHz or below, and theFCT 388915T cannot lock onto
that low of an input frequency. In the test mode described
above, any test frequency test can be used.
3052 drw 13
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT388915T70PY | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT54FCT388915T70PYB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT388915T70PYB | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE) |
| IDT74FCT807BTPYG | FAST CMOS 1-TO-10 CLOCK DRIVER |
| IDT74FCT807BTPYGI | FAST CMOS 1-TO-10 CLOCK DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT54FCT521ADB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT533DB | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT54FCT543ADB | 制造商:MAJOR 功能描述: |
| IDT54FCT543ATDB | 制造商:MAJOR 功能描述: |
| IDT54FCT573ADB | 制造商:Integrated Device Technology Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。