- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67712 > IDT5T940-30NLGI8 (INTEGRATED DEVICE TECHNOLOGY INC) 5T SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 PDF資料下載
參數(shù)資料
| 型號： | IDT5T940-30NLGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | GREEN, PLASTIC, VFQFPN-28 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 116K |
| 代理商： | IDT5T940-30NLGI8 |
1
INDUSTRIALTEMPERATURERANGE
IDT5T940
PRECISIONCLOCKGENERATOROC-192APPLICATIONS
NOVEMBER 2004
2004
Integrated Device Technology, Inc.
DSC 6195/27
c
IDT5T940
INDUSTRIAL TEMPERATURE RANGE
PRECISION CLOCK GENERATOR
OC-192 APPLICATIONS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
3-level inputs for feedback divide ratio and output frequency range
selection
1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT
Regenerated input clock or QOUT/4 on QREG
Lock indicator
Power-down mode
LVPECL or LVDS outputs
Three modes of output frequency range
- Mode 0: QOUT range 155.5 - 166.6MHz. QREG is a regenerated version
of the input clock.
- Mode 1: QOUT range 622 - 666.5MHz. QREG output 155.5-166.6MHz.
- Mode 2: QOUT range 622 - 666.5MHz. QREG is a regenerated version
of the input clock frequency.
Selectable loop bandwidths
Hitless switchover
Differential LVPECL, LVDS, or single-ended LVTTL input interface
2.375 - 3.465V core and I/O
Available in VFQFPN package
DESCRIPTION:
The IDT5T940 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
andREFINaredifferentfrequencies,themultiplicationfactorwillbeadjustedto
retain the same output frequency.
The IDT5T940 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T940-10
has LVDS outputs and the IDT5T940-30 has LVPECL outputs.
ThethreemodesofoutputfrequencyrangearecontrolledbytheSELmode,
which is a 3-level pin. When SELmode is high or low, the QOUT is a multiplied
versionoftheinputclockwhileQREGisaregeneratedversionoftheinputclock.
When SELmode is mid, the QOUT is a multiplied version of the input clock while
QREG is QOUT/4.
The IDT5T940 features a selectable loop bandwidth.
APPLICATIONS:
Terabit routers
Gigabit ethernet systems
SONET / SDH systems
Digital cross connects
Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
PLL
CONTROL
LOGIC
LOCK,
FREQ.
DETECTOR
CLKIN
REFIN
LOCK
DIVN
DIVM
QREG
QOUT
CLK/
REF0
SELMODE
PD
PLLBW1
PLLBW0
INPUT
MUX
CLKIN
REFIN
CLK/
REF1
QREG
QOUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT5T940-10NLGI | 5T SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| IDT5T9820NLGI8 | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC68 |
| IDT5T9820NLGI | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC68 |
| IDT5T9890NLI | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| IDT5T9890NLI8 | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5T9820NLGI | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9820NLGI8 | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9820NLI | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9820NLI8 | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9821NLGI | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。