- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67712 > IDT5T940-30NLGI8 (INTEGRATED DEVICE TECHNOLOGY INC) 5T SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 PDF資料下載
參數(shù)資料
| 型號： | IDT5T940-30NLGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | GREEN, PLASTIC, VFQFPN-28 |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 116K |
| 代理商： | IDT5T940-30NLGI8 |
3
INDUSTRIALTEMPERATURERANGE
IDT5T940
PRECISION CLOCKGENERATOROC-192APPLICATIONS
INPUT FREQUENCY RANGE
CLK/REF[1:0]
Input Frequency Range
H H
19.4MHz - 20.9MHz
H M
reserved
HL
38.8MHz - 41.7MHz
M H
77.7MHz - 83.4MHz
M M
AutomaticDetection
ML
155.5MHz - 167MHz
LH
311MHz - 334MHz
LM
reserved
LL
622MHz - 667MHz
PLL BANDWIDTH SELECTION
PLLBW[1:0]
Min.
Max.
Min. CLKIN/REFIN
LL
65KHz
120KHz
19.44MHz
LH
250KHz
500KHz
19.44MHz
HL
1MHz
2MHz
38.88MHz
H H
4MHz
8MHz
155.52MHz
OUTPUT FREQUENCY RANGE
SELmode
QOUT/QOUT
QREG/QREG
Unit
L
155.5-166.6
regeneratedCLKIN/CLKIN
MHz
M
622-666.5
155.5-166.6
MHz
H
622-666.5
regeneratedCLKIN/CLKIN
MHz
PIN DESCRIPTION
Pin Name
I/O
Type
Description
CLKIN, CLKIN
I
Adjustable(1)
Differentialorsingle-endedclockinputsignal. Fordifferential,LVPECLorLVDSsupported. Ifleftopen-circuited,inputswillfloat
toLVTTLthresholdvoltagesothateitherinputmaybeusedasasingle-endedinput. Acapacitortogroundshouldbeconnected
onthefloatinginput.
REFIN, REFIN
I
Adjustable(1)
Differentialreferenceclockinput. ThereferenceclockinputisusedasaninputtothePLLwhenCLKIN/CLKINfails. Differential
orsingle-endedclockinputsignal. Fordifferential,LVPECLorLVDSsupported. Ifleftopen-circuited,inputswillfloattoLVTTL
thresholdvoltagesothateitherinputmaybeusedasasingle-endedinput. Acapacitortogroundshouldbeconnectedonthe
floatinginput.
CLK/REF[1:0]
I
3-level(2)
3 level inputs controlling PLL feedback divider ratio. Automatic detection is used if both inputs are MID.
SELmode
I
3-level(2)
3levelinputtoselectoutputfrequencyrangeforQOUT/QOUT andQREG/QREG (seeOutputFrequencyRangetable)
PLLBW[1:0]
I
LVTTL
PLLBandwidthSelectInputs(seePLLBandwidthSelectiontable)
PD
I
LVTTL
Power Down Control. Shuts off entire chip when LOW.
QOUT, QOUT
0
Adjustable(3)
Differential clock output. LVPECL or LVDS outputs.
QREG, QREG
0
Adjustable(3)
Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs.
LOCK
0
LVTTL
LOW when PLL is locked to CLKIN, HIGH in all other conditions
VDD
PWR
Power Supply
GND
PWR
Ground
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V LVTTL levels
Single-ended 2.5V LVTTL levels
Differential LVPECL levels
Differential LVDS levels
2. 3-level inputs are static inputs and must be tied to VDD or GND or left floating.
3. Outputs can be LVPECL or LVDS.
LOCK
FREQUENCYDETECTOR
The 5T940 will lock to, and track, a valid CLKIN signal; LOCK will be low
when this has occurred. If CLKIN fails, the 5T940 PLL will smoothly switch
to lock to REFIN without generating any glitches on the output. The fact that
the PLL is locked to REFIN rather than CLKIN is indicated by a high state on
LOCK. When a valid input is then applied to CLKIN, the 5T940 will smoothly
switchbacktolockingonCLKIN,andLOCK willgolow. LOCK willalsoswitch
tohighshouldthefrequencyofCLKINdriftclosetothelimitsoftheVCOtuning
range.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT5T940-10NLGI | 5T SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| IDT5T9820NLGI8 | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC68 |
| IDT5T9820NLGI | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC68 |
| IDT5T9890NLI | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| IDT5T9890NLI8 | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5T9820NLGI | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9820NLGI8 | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9820NLI | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9820NLI8 | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| IDT5T9821NLGI | 功能描述:IC CLK DRIVER ZD PLL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復。