參數(shù)資料
型號: IDT5V9351PFI8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 5V SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: TQFP-32
文件頁數(shù): 8/10頁
文件大小: 96K
代理商: IDT5V9351PFI8
INDUSTRIALTEMPERATURERANGE
IDT5V9351
LOWVOLTAGEPLLCLOCKDRIVER
7
AC ELECTRICAL CHARACTERISTICS (1)
TA = -40°C to +85°C, VCC = 2.5V ± 5%
Symbol
Parameter
Conditions
Min.
Typ.
Max
Unit
tR, tF
Output Rise/Fall Time
0.6V to 1.8V
0.1
1
ns
VPP
Peak-to-PeakInputVoltage
LVPECL
500
1000
mV
VCMR
Common Mode Range(2)
LVPECL
1.2
VCC - 0.6
V
100-200 MHz
45
50
55
tPW
Output Duty Cycle
50-100 MHz
47.5
50
52.5
%
25-50 MHz
48.75
50
51.75
tSK(O)
Output to Output Skew
150
ps
fVCO
PLL VCO Lock Range
200
400
MHz
÷2output
100
200
fMAX
Maximum Output Frequency
÷4output
50
100
MHz
÷8output
25
50
tPD
Input to FBIN Delay
TCLK to FBIN
-100
100
ps
PECL_CLK to FBIN
0
300
tPLZ,tPHZ
OutputDisableTime
12
ns
tPZL,tPZH
OutputEnableTime
12
ns
÷2feedback
-3dbpointof
4 - 15
BW
PLL Closed Loop Bandwidth
÷4feedback
PLL to transfer
2 - 7
MHz
÷8feedback
characteristic
0.7 - 2
tJ
Cycle-to-Cycle Jitter
÷ 4feedback
RMS Value
10
22
ps
(SingleOutputFrequencyConfiguration)
tJIT(PER)
Period Jitter
÷4feedback
RMS Value
8
15
ps
(SingleOutputFrequencyConfiguration)
tJIT (
φ)
I/O Phase Jitter
RMS Value
6 - 25
ps
tLOCK
Maximum PLL Lock Time
1
ms
NOTES:
1. AC Characteristics apply for parallel output termination of 50
Ω to VTT.
2. VCMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within VPP(AC)
specifications.
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