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參數(shù)資料
| 型號： | IDT7016L20PFB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Quad Low-Power JFET-Input Operational Amplifier 14-SOIC 0 to 70 |
| 中文描述： | 16K X 9 DUAL-PORT SRAM, 20 ns, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 262K |
| 代理商： | IDT7016L20PFB |
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.13
19
resource is secure. As with any powerful programming
technique, if semaphores are misused or misinterpreted, a
software error can easily happen.
Initialization of the semaphores is not automatic and must
be handled via the initialization program at power-up. Since
any semaphore request flag which contains a zero must be
reset to a one, all semaphores on both sides should have a
one written into them at initialization from both sides to assure
that they will be free when needed.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7016’s Dual-Port
RAM. Say the 16K x 9 RAM was to be divided into two 8K x
9 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
used to indicate the side which would control the lower section
of memory, and Semaphore 1 could be defined as the indica-
tor for the upper section of memory.
To take a resource, in this example the lower 8K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 8K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try
and gain control of the second 8K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
side, the left side could undo its semaphore request and
perform other tasks until it was able to write, then read a zero
into Semaphore 1. If the right processor performs a similar
task with Semaphore 0, this protocol would allow the two
processors to swap 8K blocks of Dual-Port RAM with each
other.
The blocks do not have to be any particular size and can
even be variable, depending upon the complexity of the
software using the semaphore flags. All eight semaphores
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be as-
signed different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
of memory during a transfer and the I/O device cannot tolerate
any wait states. With the use of semaphores, once the two
devices has determined which memory area was “off-limits” to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces-
sors can access their assigned RAM segments at full speed.
Another application is in the area of complex data struc-
tures. In this case, block arbitration is very important. For this
application one processor may be responsible for building and
updating a data structure. The other processor then reads
and interprets that data structure. If the interpreting processor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processor to come back and read the complete data structure,
thereby guaranteeing a consistent data structure.
Figure 4. IDT7016 Semaphore Logic
D
3190 drw 20
0
D
Q
WRITE
D
0
WRITE
D
Q
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
L PORT
R PORT
SEMAPHORE
READ
SEMAPHORE
READ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7016L25G | Quad Low-Power JFET-Input Operational Amplifier 14-SOIC 0 to 70 |
| IDT7016S20G | HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM |
| IDT7016S20GB | HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM |
| IDT7016S20J | Low-Noise JFET-Input General-Purpose Operational Amplifier 8-SOIC 0 to 70 |
| IDT7016S20JB | Low-Noise JFET-Input General-Purpose Operational Amplifier 8-SOIC 0 to 70 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7016L20PFG | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L20PFGB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L20PFGI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K X 9 DUAL-PORT STATIC RAM |
| IDT7016L20PFI | 功能描述:IC SRAM 144KBIT 20NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，同步 存儲容量:1.125M（32K x 36） 速度:5ns 接口:并聯(lián) 電源電壓:3.15 V ~ 3.45 V 工作溫度:-40°C ~ 85°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-CABGA（17x17） 包裝:帶卷 (TR) 其它名稱:70V3579S5BCI8 |
| IDT7016L20PFI8 | 功能描述:IC SRAM 144KBIT 20NS 80TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
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