參數(shù)資料
型號: IDT7016L20PFB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Quad Low-Power JFET-Input Operational Amplifier 14-SOIC 0 to 70
中文描述: 16K X 9 DUAL-PORT SRAM, 20 ns, PQFP80
封裝: TQFP-80
文件頁數(shù): 8/20頁
文件大?。?/td> 262K
代理商: IDT7016L20PFB
6.13
8
IDT7016S/L
HIGH-SPEED 16K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES
(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is de-asserted first,
CE
or
OE.
3. t
BDD
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last : t
AOE
, t
ACE
, t
AA,
or t
BDD
.
5.
SEM
= V
IH
.
t
RC
R/
W
CE
ADDR
t
AA
t
ACE(4)
OE
3190 drw 07
(4)
t
AOE(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3, 4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
TIMING OF POWER-UP / POWER-DOWN
CE
3190 drw 08
t
PU
I
CC
I
SB
t
PD
50%
50%
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