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參數(shù)資料
| 型號(hào)： | IDT70V24S25G |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 4K X 16 DUAL-PORT SRAM, 25 ns, CPGA84 |
| 封裝： | 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 281K |
| 代理商： | IDT70V24S25G |
6.38
10
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
BUSY TIMING (M/
S
= V
IL
)
t
WB
BUSY
Input to Write
(4)
t
WH
Write Hold After
BUSY
(5)
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
Write Data Valid to Read Data Delay
(1)
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With
BUSY
(M /
S
= H)" or "Timing Waveform
of Write With Port-To-Port Delay (M /
S
= L)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD
is a calculated parameter and is the greater of 0ns, t
WDD
– t
WP
(actual), or t
DDD
– t
DW
(actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention with port "A".
6. "X" in part numbers indicates power rating (S or L).
0
20
—
—
0
25
—
—
0
25
—
—
ns
ns
—
55
—
60
—
80
ns
t
DDD
—
50
—
55
—
75
ns
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(6)
IDT70V24X25
IDT70V24X35
IDT70V24X55
Symbol
BUSY TIMING (M/
S
= V
IH
)
t
BAA
BUSY
Access Time from Address Match
t
BDA
BUSY
Disable Time from Address Not Matched
t
BAC
BUSY
Access Time from Chip Low
t
BDC
BUSY
Disable Time from Chip High
Arbitration Priority Set-up Time
(2)
BUSY
Disable to Valid Data
(3)
Write Hold After
BUSY
(5)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
—
—
—
—
25
25
25
25
—
—
—
—
35
35
35
35
—
—
—
—
45
45
45
45
ns
ns
ns
ns
t
APS
5
—
5
—
5
—
ns
t
BDD
—
35
—
35
—
40
ns
t
WH
20
—
25
—
25
—
ns
2911 drw 12
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/
W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD(3)
t
WDD
t
BAA
TIMING WAVEFORM OF READ WITH
BUSY
(M/
S
= V
IH
)
(2,4,5)
2740 tbl 13
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS
is ignored for M/
S
= V
IL
(slave).
2.
CE
L
=
CE
R
= V
IL
.
3.
OE
= V
IL
for the reading port.
4. If M/
S
= V
IL
(slave),
BUSY
is an input. Then for this example
BUSY
"A"
= V
IH
and
BUSY
"B"
input is shown above.
5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".
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| IDT70V24S25J | 功能描述:IC SRAM 64KBIT 25NS 84PLCC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
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