參數(shù)資料
型號(hào): IDT70V24S25G
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
中文描述: 4K X 16 DUAL-PORT SRAM, 25 ns, CPGA84
封裝: 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84
文件頁(yè)數(shù): 7/17頁(yè)
文件大?。?/td> 281K
代理商: IDT70V24S25G
6.38
7
IDT70V24S/L
HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
(5)
IDT70V24X25
IDT70V24X35
IDT70V24X55
Symbol
WRITE CYCLE
t
WC
t
EW
t
AW
t
AS
t
WP
t
WR
t
DW
t
HZ
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Write Cycle Time
Chip Enable to End-of-Write
(3)
Address Valid to End-of-Write
Address Set-up Time
(3)
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
(1, 2)
Data Hold Time
(4)
Write Enable to Output in High-Z
(1, 2)
Output Active from End-of-Write
(1, 2, 4)
25
20
20
0
20
0
15
15
35
30
30
0
25
0
20
20
55
45
45
0
40
0
30
25
ns
ns
ns
ns
ns
ns
ns
ns
t
DH
0
0
0
ns
t
WZ
15
20
25
ns
t
OW
0
0
0
ns
t
SWRD
SEM
Flag Write to Read Time
5
5
5
ns
t
SPS
SEM
Flag Contention Window
5
5
5
ns
WAVEFORM OF READ CYCLES
(5)
t
RC
R/
W
CE
ADDR
t
AA
t
ACE(4)
OE
UB
,
LB
2911 drw 07
(4)
t
AOE(4)
t
ABE(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3, 4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
NOTES:
1. Timing depends on which signal is asserted last,
OE
,
CE
,
LB
, or
UB
.
2. Timing depends on which signal is de-asserted firs
CE
,
OE
,
LB
, or
UB
.
3. t
BDD
delay is required only in cases where opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
ABE
, t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
NOTES:
1. Transition is measured
±
200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM,
CE
= V
IL
,
UB
or
LB
= V
IL
,
SEM
= V
IH
. To access semaphore,
CE
= V
IH
and
SEM
= V
IL
. Either condition must be valid for the entire t
EW
time.
4. The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
OW
values will vary
over voltage and temperature, the actual t
DH
will always be smaller than the actual t
OW
.
5. "X" in part numbers indicates power rating (S or L).
2911 tbl 12
相關(guān)PDF資料
PDF描述
IDT70V24S25J HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
IDT70V24S25PF HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
IDT70V24S35G HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
IDT70V24S35J HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
IDT70V24S35PF HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
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