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參數(shù)資料
| 型號(hào)： | IDT70V26S55JI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 3.3V 16K x 16 DUAL-PORT STATIC RAM |
| 中文描述： | 高速3.3 16K的× 16 DUAL-PORT靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 13/17頁(yè) |
| 文件大小： | 144K |
| 代理商： | IDT70V26S55JI |
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6.42
IDT70V26S/L
High-Speed 16K x 16 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
BUSY
/&
Inputs
Outputs
The IDT70V26 provides two ports with separate control, address
and I/O pins that permt independent access for reads or writes to any
location in memory. The IDT70V26 has an automatic power down
feature controlled by
CE
. The
CE
controls on-chip power down circuitry
that permts the respective port to go into a standby mode when not
selected (
CE
HIGH). When a port is enabled, access to the entire
memory array is permtted.
3B
Busy Logic provides a hardware indication that both ports of the
RAMhave accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAMis
“
busy
”
. The
BUSY
pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted fromthe side that receives a
BUSY
indication, the
write signal is gated internally to prevent the write fromproceeding.
The use of
BUSY
logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the
BUSY
outputs
together and use any
BUSY
indication as an interrupt source to flag an
illegal or illogical operation. If the write inhibit function of
BUSY
logic is
not desirable, the
BUSY
logic can be disabled by placing the part in
slave mode with the M/
S
pin. Once in slave mode the
BUSY
pin
operates solely as a write inhibit input pin. Normal operation can be
programmed by tying the
BUSY
pins HIGH. If desired, unintended
NOTES:
1.
Pins
BUSY
L
and
BUSY
R
are both outputs when the part is configured as a master. Both are inputs when configured as a slave.
BUSY
X
outputs on the IDT70V26 are push
pull, not open drain outputs. On slaves the
BUSY
X
input internally inhibits writes.
L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable
inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will result.
BUSY
L
and
BUSY
R
outputs cannot be LOW simultaneously.
Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSY
R
outputs are driving LOW regardless of actual logic level on the pin.
2.
3.
$%$&'''(/++
$%$&'4(1)%)C
!
NOTE:
1.
2.
3.
This table denotes a sequence of events for only one of the eight semaphores on the IDT70V26.
There are eight semaphore flags written to via I/O
0
and read fromall I/O's (I/O
0
-I/O
15
). These eight semaphores are addressed by A
0
-A
2
.
CE
= V
IH
,
SEM
= V
IL
to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Function
CE
L
CE
R
A
0L
-A
13L
A
0R
-A
13R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
2945 tbl 14
Functions
D
0
- D
15
Left
D
0
- D
15
Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
2945 tbl 15
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