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參數(shù)資料
| 型號： | IDT7198L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Current-Mode PWM Controller 8-SOIC -40 to 85 |
| 中文描述： | 64K的的CMOS靜態(tài)RAM（16K的× 4位）新增芯片選擇和輸出控制 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 80K |
| 代理商： | IDT7198L |
6.4
5
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
NOTES:
1.
WE
is HIGH for Read cycle.
2. Device is continuously selected,
CS
1
is LOW,
CS
2
is LOW.
3. Address valid prior to or coincident with
CS
1
and or
CS
2
transition LOW.
4.
OE
is LOW.
5. Transition is measured
±
200mV from steady state voltage.
TIMING WAVEFORM OF READ CYCLE NO. 1
(1)
ADDRESS
CS
1, 2
DATA
OUT
OE
2985 drw 07
t
RC
t
AA
t
OH
t
ACS1, 2
t
CLZ1, 2(5)
t
CHZ1, 2(5)
t
OE
t
OLZ(5)
t
OHZ(5)
DATA VALID
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
10%, Military Temperature Range)
7198S20
7198L20
Symbol
Parameter
Min. Max. Min.
7198S25
7198L25
7198S35/45
7198L35/45
7198S55
7198L55
7198S70
7198L70
7198S85
7198L85
Max. Min. Max. Min. Max. Min.
Max. Min. Max. Unit
Read Cycle
t
RC
Read Cycle Time
20
—
25
—
35/45
—
55
—
70
—
85
—
ns
t
AA
t
ACS1,2(1)
Chip Select-1,2 Access Time
t
CLZ1,2(2)
Chip Select-1,2 to Output in Low-Z
Address Access Time
—
19
—
25
—
35/45
—
55
—
70
—
85
ns
—
20
—
25
—
35/45
—
55
—
70
—
85
ns
5
—
5
—
5
—
5
—
5
—
5
—
ns
t
OE
t
OLZ(2)
t
CHZ1,2(2)
Chip Select 1,2 to Output in High-Z
t
OHZ(2)
Output Disable to Output in High-Z
Output Enable to Output Valid
—
9
—
11
—
20/25
—
35
—
45
—
55
ns
Output Enable to Output in Low-Z
5
—
5
—
5
—
5
—
5
—
5
—
ns
—
8
—
10
—
14
—
20
—
25
—
30
ns
—
8
—
9
—
15
—
20
—
25
—
30
ns
t
OH
t
PU(2)
t
PD(2)
Output Hold from Address Change
5
—
5
—
5
—
5
—
5
—
5
—
ns
Chip Select to Power Up Time
0
—
0
—
0
—
0
—
0
—
0
—
ns
Chip Deselect to Power Down Time
—
20
—
25
—
35/45
—
55
—
70
—
85
ns
NOTES:
1. Both chip selects must be active low for the device to be selected.
2. This parameter is guaranteed by device characterization but is not production tested.
2985 tbl 11
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