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參數(shù)資料
| 型號(hào)： | IDT7198L |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Current-Mode PWM Controller 8-SOIC -40 to 85 |
| 中文描述： | 64K的的CMOS靜態(tài)RAM（16K的× 4位）新增芯片選擇和輸出控制 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 80K |
| 代理商： | IDT7198L |
6.4
7
IDT7198S/L
CMOS STATIC RAMS 64K (16K x 4-BIT) Added Chip Select and Output Enable Controls
MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 3, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1)
NOTES:
1.
WE
,
CS
1
or
CS
2
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
WE
, a LOW
CS
1
and a LOW
CS
2
.
3. t
WR
is measured from the earlier of
CS
1
,
CS
2
or
WE
going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, outputs remain in the high-impedance state.
6. Transition is measured
±
200mV from steady state.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified t
WP
.
CS
1, 2
DATA
IN
ADDRESS
WE
DATA
OUT
OE
2985 drw 10
t
AW
t
WR
t
DW
t
WC
t
WP
t
DH
t
WHZ
t
OW
t
AS
(6)
(6)
(4)
(4)
(7)
DATA VALID
CS
1, 2
DATA
IN
ADDRESS
WE
t
WR
2985 drw 11
t
AW
t
DW
t
WC
t
CW
t
DH
t
AS
DATA VALID
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