參數(shù)資料
型號(hào): IDT71V25761S166BQI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
中文描述: 128K X 36 CACHE SRAM, 3.5 ns, PBGA165
封裝: FBGA-165
文件頁(yè)數(shù): 9/23頁(yè)
文件大?。?/td> 526K
代理商: IDT71V25761S166BQI
6.42
IDT71V25761, IDT71V25781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V ± 5%)
Symbol
Parameter
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load
AC Test Conditions
(V
DDQ
= 2.5V)
NOTE:
1. The
LBO
pin will be internally pulled to V
DD
if it is not actively driven in the application and the ZZ pin will be internally pulled to V
SS
if not actively driven.
NOTES:
1. All values are maximumguaranteed values.
2. At f = f
MAX,
inputs are cycling at the maximumfrequency of read cycles of 1/t
CYC
while
ADSC
= LOW; f=0 means no input lines are changing.
3. For I/Os V
HD
= V
DDQ
- 0.2V, V
LD
= 0.2V. For other inputs V
HD
= V
DD
- 0.2V, V
LD
= 0.2V.
V
DDQ
/2
50
I/O
Z
0
= 50
5297 drw 06
,
1
2
3
4
20 30 50
100
200
5297 drw 07
,
(TyptCD
Capacitance (pF)
80
5
6
Test Conditions
Mn.
Max.
Unit
|
LI
|
Input Leakage Current
V
DD
= Max., V
IN
= 0V to V
DD
___
5
μA
|
LZZ
|
ZZ and
LBO
Input Leakage Current
(1)
V
DD
= Max., V
IN
= 0V to V
DD
___
30
μA
|
LO
|
Output Leakage Current
V
OUT
= 0V to V
DDQ
, Device Deselected
___
5
μA
V
OL
Output LowVoltage
I
OL
= +6mA, V
DD
= Mn.
___
0.4
V
V
OH
Output High Voltage
I
OH
= -6mA, V
DD
= Mn.
2.0
___
V
5297 tbl 08
Symbol
Parameter
Test Conditions
200MHz
183MHz
166MHz
Unit
Com'l Only
Com'l
Ind
Com'l
Ind
I
DD
Operating Power Supply
Current
Device Selected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
360
340
350
320
330
mA
I
SB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = 0
(2,3)
30
30
35
30
35
mA
I
SB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, V
DD
= Max.,
V
DDQ
= Max., V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
130
120
130
110
120
mA
I
ZZ
Full Sleep Mode Supply
Current
ZZ > V
HD
V
DD
= Max.
30
30
35
30
35
mA
5297 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timng Reference Levels
Output Timng Reference Levels
AC Test Load
0 to 2.5V
2ns
(V
DDQ
/2)
(V
DDQ
/2)
See Figure 1
5297 tbl 10
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