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參數(shù)資料
| 型號： | IDT71V3548S133PFI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs |
| 中文描述： | 256K X 18 ZBT SRAM, 4.2 ns, PQFP100 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 494K |
| 代理商： | IDT71V3548S133PFI |
MAY 2002
DSC-5296/03
1
2002 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAMS. They are designed to elimnate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
TM
, or
Zero Bus Turnaround.
Features
N
256K x 18 memory configurations
N
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
N
ZBT
TM
Feature - No dead cycles between write and read
cycles
N
Internally synchronized output buffer enable eliminates the
need to control
OE
N
Single R/
W
(READ/WRITE) control pin
N
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
N
4-word burst capability (interleaved or linear)
N
Individual byte write (
BW
1
-
BW
4
) control (May tie active)
N
Three chip enables for simple depth expansion
N
3.3V power supply (±5%), 3.3V I/O Supply (V
DDQ)
N
Optional Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
N
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
A
0
-A
17
Address Inputs
Input
Synchronous
CE
1
, CE
2
,
CE
2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O
0
-I/O
15
, I/O
P1
-I/O
P2
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power I/O Power
Supply
Static
V
SS
Ground
Supply
Static
5296 tbl 01
IDT71V3548S
IDT71V3548SA
256K x 18
3.3V Synchronous ZBT SRAM
3.3V I/O, Burst Counter
Pipelined Outputs
Address and control signals are applied to the SRAMduring one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3548 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (
CEN
) pin allows operation of the IDT71V3548
to be suspended as long as necessary. All synchronous inputs are
ignored when (
CEN
) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (
CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/
LD
is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
The IDT71V3548 has an on-chip burst counter. In the burst
mode, the IDT71V3548 can provide four cycles of data for a single address
presented to the SRAM The order of the burst sequence is defined by the
LBO
input pin. The
LBO
pin selects between linear and interleaved burst
sequence. The ADV/
LD
signal is used to load a new external address
(ADV/
LD
= LOW) or increment the internal burst counter (ADV/
LD
=
HIGH).
The IDT71V3548 SRAMs utilize IDT's latest high-performance CMOS
process and are packaged in a JEDEC standard 14mmx 20mm100- pin
plastic thin quad flatpack (TQFP) as well as a 119 ball grid array (BGA)
and 165 fine pitch ball grid array (fBGA).
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| IDT71V3548SA | 256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs |
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| IDT71V3548SA100BGI | 256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs |
| IDT71V3548SA100BQ | 256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs |
| IDT71V3548SA100BQI | 256K x 18 3.3V Synchronous ZBT SRAM 3.3V I/O, Burst Counter Pipelined Outputs |
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| IDT71V3556S100BG | 功能描述:IC SRAM 4MBIT 100MHZ 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V3556S100BG8 | 功能描述:IC SRAM 4MBIT 100MHZ 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V3556S100BGI | 功能描述:IC SRAM 4MBIT 100MHZ 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V3556S100BGI8 | 功能描述:IC SRAM 4MBIT 100MHZ 119BGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
| IDT71V3556S100BQ | 功能描述:IC SRAM 4MBIT 100MHZ 165FBGA RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 產(chǎn)品變化通告:Product Discontinuation 05/Nov/2008 標準包裝:84 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 ZBT 存儲容量:4.5M（128K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:119-BGA 供應商設備封裝:119-PBGA（14x22） 包裝:托盤 其它名稱:71V3557SA75BGI |
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