參數(shù)資料
型號: IDT71V67902S80PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
中文描述: 512K X 18 CACHE SRAM, 8 ns, PQFP100
封裝: 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
文件頁數(shù): 11/23頁
文件大?。?/td> 527K
代理商: IDT71V67902S80PF
6.42
11
IDT71V67702, IDT71V67902, 256K x 36, 512K x 18, 3.3V Synchronous Commercial and Industrial Temperature Ranges
SRAMs with 2.5V I/O, Flow-Through Outputs, Single Cycle Deselect
Linear Burst Sequence Table (
LBO
=V
SS
)
Synchronous Write Function Truth Table
(1, 2)
GW
Asynchronous Truth Table
(1)
Interleaved Burst Sequence Table (
LBO
=V
DD
)
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2.
BW
3
and
BW
4
are not applicable for the IDT71V67902.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation
BWE
BW
1
BW
2
BW
3
BW
4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
Write Byte 1
(3)
H
L
L
H
H
H
Write Byte 2
(3)
H
L
H
L
H
H
Write Byte 3
(3)
H
L
H
H
L
H
Write Byte 4
(3)
H
L
H
H
H
L
5317 tbl 12
Operation
(2)
OE
ZZ
I/O Status
Power
Read
L
L
Data Out
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z – Data In
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
5317 tbl 13
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address
(1)
1
1
1
0
0
1
0
0
5317 tbl 14
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address
(1)
1
1
0
0
0
1
1
0
5317 tbl 15
相關(guān)PDF資料
PDF描述
IDT71V67902S80PFI 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
IDT71V67902S85BG 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
IDT71V67902S85BGI 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
IDT71V67902S85BQ 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
IDT71V67902S85BQI 256K X 36, 512K X 18 3.3V Synchronous SRAMs 2.5V I/O, Burst Counter Flow-Through Outputs, Single Cycle Deselect
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