參數(shù)資料
型號(hào)： IDT72261LA15TF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 25/27頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 8192X18 LP 15NS 64QFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 7200
功能： 同步
存儲(chǔ)容量： 144K（8K x 18）
數(shù)據(jù)速率： 67MHz
訪問(wèn)時(shí)間： 15ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 72261LA15TF8
7
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72261LA/72271LA SuperSync FIFO
16,384 x 9 and 32,768 x 9
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause
the FIFO to become empty. When the last word has been read from the
FIFO, the EF will go LOW inhibiting further read operations. REN is ignored
when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the
8,194th word for the IDT72261LA and 16,386th word for the IDT72271LA,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAF will go LOW after (16,385-m) writes for the IDT72261LA and (32,769-
m) writes for the IDT72271LA, where m is the full offset value. The default
setting for this value is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 16,385 writes for the 72261LA and
32,769 writes for the IDT72271LA, respectively. Note that the additional
word in FWFT mode is due to the capacity of the memory plus output
register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is
ignored when the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72261LA/72271LA support two different timing modes of opera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset,
by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whether or not there are any words present in the FIFO. It also uses the Full
Flag function (FF) to indicate whether or not the FIFO has any free space
for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using the Read Enable (REN) and
RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR)
to indicate whether or not the FIFO has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently de-
pending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After
the first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 8,193th word for IDT72261LA and 16,385th word for IDT72271LA
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.
Again, if no reads are performed, the PAF will go LOW after (16,384-m)
writes for the IDT72261LA and (32,768-m) writes for the IDT72271LA. The
offset “m” is the full offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 16,384 writes for the IDT72261LA and
32,768 for the IDT72271LA, respectively.
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IDT72261LA15TFGI8 功能描述:IC FIFO 8192X18 LP 15NS 64QFP RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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