參數(shù)資料
型號(hào): IDT72261LA15TFI8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 1/27頁(yè)
文件大?。?/td> 0K
描述: IC FIFO 8192X18 LP 15NS 64QFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 7200
功能: 同步
存儲(chǔ)容量: 144K(8K x 18)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 72261LA15TFI8
1
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4671/5
JULY 2013
IDT, IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72261LA
IDT72271LA
CMOS SuperSync FIFO
16,384 x 9
32,768 x 9
FEATURES:
Choose among the following memory organizations:
IDT72261LA 16,384 x 9
IDT72271LA 32,768 x 9
Pin-compatible with the IDT72281/72291 SuperSync FIFOs
10ns read/write cycle time (8ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
16,384 x 9
32,768 x 9
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D0 -D8
LD
MRS
REN
RCLK
OE
Q0 -Q8
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
4671 drw 01
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
The period required by the retransmit operation is now fixed and short.
The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is now fixed and short. (The
variableclockcyclecountingdelayassociatedwiththelatencyperiodfound
on previous SuperSync devices has been eliminated on this SuperSync
family.)
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