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參數(shù)資料
型號(hào)： IDT72261LA15TFI8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 21/27頁(yè)
文件大?。?/td> 0K
描述： IC FIFO 8192X18 LP 15NS 64QFP
標(biāo)準(zhǔn)包裝： 1,250
系列： 7200
功能： 同步
存儲(chǔ)容量： 144K（8K x 18）
數(shù)據(jù)速率： 67MHz
訪問(wèn)時(shí)間： 15ns
電源電壓： 4.5 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 帶卷 (TR)
其它名稱： 72261LA15TFI8
3
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72261LA/72271LA SuperSync FIFO
16,384 x 9 and 32,768 x 9
DESCRIPTION (CONTINUED)
Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
MASTER RESET (
MRS)
READ CLOCK (RCLK)
READ ENABLE (
REN)
OUTPUT ENABLE (
OE)
EMPTY FLAG/OUTPUT READY (
EF/OR)
PROGRAMMABLE ALMOST-EMPTY (
PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
LOAD (
LD)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE ALMOST-FULL (
PAF)
IDT
72261LA
72271LA
PARTIAL RESET (
PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (
RT)
4671 drw 03
HALF FULL FLAG (
HF)
SERIAL ENABLE(
SEN)
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for
access. The state of the FWFT/SI input during Master Reset determines
the timing mode in use.
For applications requiring more data storage capacity than a single
FIFO can provide, the FWFT timing mode permits depth expansion by
chaining FIFOs in series (i.e. the data outputs of one FIFO are connected
to the corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF
and FF functions are selected in IDT Standard mode. The IR and OR
functions are selected in FWFT mode. HF, PAE and PAF are always
available for use, irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point
in memory. (See Table I and Table II.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that PAE can be
set to switch at 127 or 1,023 locations from the empty boundary and the
PAF threshold can be set at 127 or 1,023 locations from the full boundary.
These choices are made with the LD pin during Master Reset.
For serial programming, SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,
areusedtoloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrising
edge of RCLK can be used to read the offsets in parallel from Qn regardless
of whether serial or parallel offset loading has been selected.
DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
withserialprogramming. Theflagsareupdatedaccordingtothetimingmode
anddefaultoffsetsselected.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in
mid-operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the
memory array.
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
The IDT72261LA/72271LA are fabricated using high speed submicron
CMOStechnology.
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參數(shù)描述
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