1. t
參數(shù)資料
型號: IDT723623L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 17/28頁
文件大小: 0K
描述: IC FIFO SYNC 1KX9 15NS 128QFP
標準包裝: 1,000
系列: 7200
功能: 同步
存儲容量: 9K(1K x 9)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723623L15PF8
24
COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for
FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then
FF may transition HIGH one CLKA cycle later than shown.
2. If Port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively.
Figure 14.
FF
FF Flag Timing and First Available Write when FIFO is Full (IDT Standard Mode)
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for
AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then
AE may transition HIGH one CLKB cycle later than shown.
2. FIFO Write (
CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO.
3. If Port B size is word or byte,
AE is set LOW by the last word or byte read from the FIFO, respectively.
Figure 15. Timing for
AE
AE when the FIFO is Almost-Empty (IDT Standard and FWFT Modes).
AE
CLKA
ENB
3269 drw16
ENA
CLKB
2
1
tENS2
tENH
tSKEW2(1)
tPAE
tENS2
tENH
X Word in FIFO
(X+1) Words in FIFO
CSB
EF
W/RB
MBB
ENB
B0-B35
CLKB
FF
CLKA
CSA
3269 drw15
W/RA
A0-A35
MBA
ENA
12
tCLK
tCLKH
tCLKL
tENS2
tENH
tA
tSKEW1
tCLK
tCLKL
tENS2
tDS
tENH
tDH
To FIFO
Previous Word in FIFO Output Register
Next Word From FIFO
LOW
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO Full
WFF
t
tCLKH
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