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參數資料
| 型號： | IDT723623L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 1KX9 15NS 128QFP |
| 標準包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 9K（1K x 9） |
| 數據速率： | 67MHz |
| 訪問時間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應商設備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723623L15PF8 |
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COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
TABLE 4 — FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
Number of Words in FIFO(1,2)
to CLKB
to CLKA
IDT723623(3)
IDT723633(3)
IDT723643(3)
EF/OR
AE
AF
FF/IR
000
L
H
1 to X
H
L
H
(X+1) to [256-(Y+1)]
(X+1) to [512-(Y+1)]
(X+1) to [1,024-(Y+1)]
H
(256-Y) to 255
(512-Y) to 511
(1,024-Y) to 1,023
H
L
H
256
512
1,024
H
L
NOTES:
1.
When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2.
Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output
register (no read operation necessary), it is not included in the memory count.
3.
X is the almost-empty offset used by
AE. Y is the almost-full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
can be programmed from 1 to 508 (IDT723623), 1 to 1,020 (IDT723633), or
1 to 2,044 (IDT723643).
Whentheoptiontoprogramtheoffsetregistersseriallyischosen,theFull/
Input Ready (
FF/IR)flagremainsLOWuntilallregisterbitsarewritten.FF/IR
is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
See Figure 6, Serial Programming of the Almost-Full Flag and Almost-
Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes).
FIFO WRITE/READ OPERATION
ThestateofthePortAdata(A0-A35)linesiscontrolledbyPortAChipSelect
(
CSA)andPortAWrite/ReadSelect(W/RA). TheA0-A35linesareintheHigh-
impedancestatewheneither
CSAorW/RAisHIGH. TheA0-A35linesareactive
outputs when both
CSA and W/RA are LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW,and
FF/IRisHIGH(seeTable2). FIFOwritesonPortAareindependent
of any concurrent reads on Port B.
ThePortBcontrolsignalsareidenticaltothoseofPortAwiththeexception
thatthePortBWrite/Readselect(
W/RB)istheinverseofthePortAWrite/Read
select (W/
RA). ThestateofthePortBdata(B0-B35)linesiscontrolledbythe
Port B Chip Select (
CSB)andPortBWrite/Readselect(W/RB). TheB0-B35
linesareinthehigh-impedancestatewheneither
CSBisHIGHorW/RBisLOW.
The B0-B35 lines are active outputs when
CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when
CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is
LOW, and
EF/OR is HIGH (see Table 3). FIFO reads on Port B are
independent of any concurrent writes on Port A.
The setup and hold time constraints to the port clocks for the port Chip
SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations
andarenotrelatedtohigh-impedancecontrolofthedataoutputs. Ifaportenable
is LOW during a clock cycle, the port’s Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is
LOW, the next word written is automatically sent to the FIFO’s output register
bytheLOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflag
HIGH. WhentheOutputReadyflagisHIGH,dataresidingintheFIFO’smemory
array is clocked to the output register only when a read is selected using the
port’s Chip Select, Write/Read select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, regardless of whether
the Empty Flag is LOW or HIGH, data residing in the FIFO’s memory array is
clockedtotheoutputregisteronlywhenareadisselectedusingtheport’sChip
Select, Write/Read select, Enable, and Mailbox select. Port A Write timing
diagram can be found in Figure 7. Relevant port B Read timing diagrams
together with Bus-Matching and Endian select can be found in Figure 8, 9 and
10.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. Thisisdonetoimproveflag-signalreliabilitybyreducingtheprobability
of metastable events when CLKA and CLKB operate asynchronously to one
another.
FF/IR, and AF are synchronized to CLKA. EF/OR and AE are
synchronized to CLKB. Table 4 shows the relationship of each port flag to the
number of words stored in memory.
EMPTY/OUTPUT READY FLAGS (
EF/OR)
Thesearedualpurposeflags. IntheFWFTmode,theOutputReady(OR)
functionisselected. WhentheOutput-ReadyflagisHIGH,newdataispresent
in the FIFO output register. When the Output Ready flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
IntheIDTStandardmode,theEmptyFlag(
EF)functionisselected. When
the Empty Flag is HIGH, data is available in the FIFO’s memory for reading to
the output register. When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data from its array (CLKB). For both the FWFT and IDT Standard
modes, the FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an Output Ready flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in
memory is the next data to be sent to the FlFO output register and three cycles
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
outputregister.
In IDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
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