參數(shù)資料
型號(hào): IDT723626L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 27/35頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 256X36X2 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲(chǔ)容量: 18.4K(256 x 36 x 2)
數(shù)據(jù)速率: 67MHz
訪問時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723626L15PF8
33
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
Figure 28. Timing for Mail1 Register and
MBF1
MBF1 Flag (IDT Standard and FWFT Modes)
NOTE:
1. If Port B is configured for word size, data can be written to the Mail1 register using A0-A17 (A18-A35 are don't care inputs). In this first case B0-B17 will have valid data. If Port B is configured
for byte size, data can be written to the Mail1 Register using A0-A8 (A9-A35 are don't care inputs). In this second case, B0-B8 will have valid data (B9-B17 will be indeterminate).
3271 drw29
CLKA
ENA
A0-A35
MBA
CSA
W/RA
CLKB
MBF1
CSB
MBB
RENB
B0-B17
W1
tENH
tDS
tDH
tPMF
tENH
tDIS
tEN
tMDV
tPMR
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
tENH
tENS1
tENS2
Figure 29. Timing for Mail2 Register and
MBF2
MBF2 Flag (IDT Standard and FWFT Modes)
NOTE:
1. If Port C is configured for word size, data can be written to the Mail2 register using C0-C17. In this first case, A18-A35 will have valid data (A0-A17 will be indeterminate). If Port C is configured
for byte size, data can be written to the Mail2 register using C0-C8 (C9-C17 are don't care inputs). In this second case, A18-A26 will have valid data (A0-A17 and A27-A35 will be
indeterminate).
3271 drw30
CLKC
ENC
C0-C17
MBC
CLKA
MBF2
CSA
MBA
ENA
A0-A35
W/RA
W1
tDS
tDH
tPMF
tENH
tDIS
tEN
tMDV
tPMR
FIFO2 Output Register
W1 (Remains valid in Mail2 Register after read)
tENH
tENS2
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