參數(shù)資料
型號: IDT723626L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 33/35頁
文件大小: 0K
描述: IC FIFO SYNC 256X36X2 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲容量: 18.4K(256 x 36 x 2)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723626L15PF8
7
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723626/723636/723646 with CLKA,
CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT723626/723636/
723646 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x
ICC x dc)] + Σ(CL x VCC2 X fo)
N
where:
N
=
number of inputs driven by TTL levels
ICC =
increase in power supply current for each input at a TTL HIGH level
dc
=
duty cycle of inputs at a TTL HIGH level of 3.4V
CL
=
output capacitance load
fo
=
switching frequency of an output
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
010
20
30
40
50
60
70
0
50
100
250
300
VCC = 5.5V
3271 drw02a
200
150
80
90
VCC = 4.5V
VCC = 5.0V
fdata = 1/2 fS
TA = 25
°C
CL = 0 pF
fS
Clock Frequency MHz
ICC(f)
Supply
Current
mA
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