參數(shù)資料
型號: IDT723631L20PFI8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 12/21頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 512X36 120-TQFP
標(biāo)準(zhǔn)包裝: 750
系列: 7200
功能: 同步
存儲容量: 18.4K(512 x 36)
數(shù)據(jù)速率: 50MHz
訪問時間: 20ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 120-LQFP
供應(yīng)商設(shè)備封裝: 120-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 723631L20PFI8
2
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1,024 x 36 and 2,048 x 36
DESCRIPTION (CONTINUED)
NOTES:
1. NC – No Connection
2. Uses Yamaichi socket IC51-1324-828
PQFP (PQ132-1, ORDER CODE: PQF)
TOP VIEW
PIN CONFIGURATION
NC
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
NC
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
3023 drw02
117
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
NC
NC B
11
B
10
B
9
B
7
B
8
V
CC
B
6
GND
B
5
B
4
B
3
B
2
B
1
B
0
GND
A
0
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
NC
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
NC
NC V
CC
CLKB
ENB
W
/RB
CSB GND
RFM
RTM
V
CC
MBF1
MBB
FS1/
SEN
GND
FS0/SD
RST MBA MBF2
AE AF V
CC
IR
CSA
W/
R
A
ENA
CLKA
GND
NC
V
CC
OR
*
register has a flag to signal when new mail has been stored. Two or more
devices may be used in parallel to create wider data paths. Expansion is
also possible in word depth.
These devices are a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the
LOW-to-HIGH transition of a continuous (free-running) port clock by en-
able signals. The continuous clocks for each port are independent of one
another and can be asynchronous or coincident. The enables for each
port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The Input Ready (IR) flag and Almost-Full (
AF) flag of the FIFO are
two-stage synchronized to CLKA. The Output Ready (OR) flag and Al-
most-Empty (
AE) flag of the FIFO are two-stage synchronized to CLKB.
Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be
programmed from port A or through a serial input.
* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
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