參數(shù)資料
型號: IDT723643L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/28頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 1024X36 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲容量: 36.8K(1K x 36)
數(shù)據(jù)速率: 67MHz
訪問時間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723643L15PF8
1
2009 Integrated Device Technology, Inc.
All rights reserved. Product specifications subject to change without notice.
DSC-3269/4
FEBRUARY 2009
CMOS BUS-MATCHING SyncFIFOTM
256 x 36, 512 x 36, 1,024 x 36
IDT723623
IDT723633
IDT723643
COMMERCIAL TEMPERATURE RANGE
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
FEATURES:
Memory storage capacity:
IDT723623
256 x 36
IDT723633
512 x 36
IDT723643
1,024 x 36
Clocked FIFO buffering data from Port A to Port B
Clock frequencies up to 83 MHz (8 ns access time)
IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts available, see ordering information
DESCRIPTION:
TheIDT723623/723633/723643aremonolithic,high-speed,low-power,
CMOS unidirectional Synchronous (clocked) FIFO memories which support
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Programmable Flag
Offset Registers
Status Flag
Logic
EF/OR
AE
36
FF/IR
AF
36
Timing
Mode
FWFT
A0-A35
SPM
FS0/SD
FS1/SEN
B0-B35
Write
Pointer
Read
Pointer
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
10
3269 drw01
Input
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
FIFO1
Mail1,
Mail2,
Reset
Logic
RS1
MBF1
36
Bus-
Matching
Output
Register
PRS
36
RS2
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