35
COMMERCIALTEMPERATURERANGE
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
CLKA
RENB
CLKB
RT1
5611 drw31
tRSTS
tRSTH
tREF
(2)
B0-Bn
RTM
EFB
tREF
(2)
W1
Wx
13
4
2
1
34
2
tRTMS
tRTMH
tA
tENS2
tENH
NOTES:
1.
CSB = LOW
2. Retransmit setup is complete after
EFB returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO1.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO1 (Master or Partial) and Retransmit setup. Therefore,
FFA will be LOW throughout the Retransmit
setup procedure. D = 2,048, 4,096 and 8,192 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 30. Retransmit Timing for FIFO1 (IDT Standard Mode)
NOTES:
1.
CSA = LOW
2. Retransmit setup is complete after
EFA returns HIGH, only then can a read operation begin.
3. W1 = first word written to the FIFO1 after Master Reset on FIFO2.
4. No more than D-2 may be written to the FIFO1 between Reset of FIFO2 (Master or Partial) and Retransmit setup. Therefore,
FFC will be LOW throughout the Retransmit
setup procedure. D = 2,048, 4,096 and 8,192 for the IDT723656, IDT723666 and IDT723676 respectively.
Figure 31. Retransmit Timing for FIFO2 (IDT Standard Mode)
CLKC
ENA
CLKA
RT2
5611 drw32
tRSTS
tRSTH
tREF
(2)
A0-An
RTM
EFA
W1
Wx
tRTMS
tRTMH
tREF
(2)
13
4
2
1
34
2
tA
tENS2
tENH