37
COMMERCIALTEMPERATURERANGE
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
5611 drw35
CLKA
ENA
MBA
CSA
W/RA
tCLK
tCLKH
tCLKL
tA
tMDV
tEN
tA
tENS2
tENH
tDIS
No Operation
Wn(1)
Wn+1
LOOP
Wn-1(1)
A0-A35
Write to FIFO 1
tENS2
NOTES:
1. Data is read from FIFO2 and written into FIFO1 & placed on Port A simultaneously. The first data word written into FIFO1 is the Previous Data Word (Wn-1)
2. All FIFO status flags operate as normal, based on the contents of respective FIFO's.
3. Loopback is available in both Standard IDT and FWFT modes. The diagram above is for both.
Figure 34. Loopback Operation (FIFO2 data transfer to FIFO1 and Port A)
5611 drw36
CLKA
ENA
MBA
CSA
W/RA
tCLK
tCLKH
tCLKL
tENS2
tA
tMDV
tEN
tA
tENH
tDIS
No Operation
Wn(1)
Wn+1
A0-A35
LOOP
(4) WRITE
to FIFO 1
HIGH-Z
Wn-1(1)
Write to FIFO 1
tENS2
NOTES:
1. Data is read from FIFO2 and written into FIFO1 only. The data from FIFO2 is NOT placed on Port A. Port A is held in the high impedance state.
2. All FIFO status flags operate as normal, based on the contents of respective FIFO's.
3. Loopback is available in both Standard IDT and FWFT modes. The diagram above is for both.
4. Write operations to FIFO1 cannot be accessed via Port A.
Figure 35. Loopback Operation (FIFO2 data transfer to FIFO1)