IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH BUS MATCHING 2,048 x 3" />
參數(shù)資料
型號(hào): IDT723676L12PF
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 38/39頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 16384X36 128QFP
標(biāo)準(zhǔn)包裝: 36
系列: 7200
功能: 同步
存儲(chǔ)容量: 576K(16K x 36)
數(shù)據(jù)速率: 83MHz
訪問(wèn)時(shí)間: 12ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤(pán)
其它名稱(chēng): 723676L12PF
8
IDT723656/723666/723676 CMOS TRIPLE BUS SyncFIFOTM WITH
BUS MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIALTEMPERATURERANGE
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
0
10
20
3040
5060
70
0
50
100
150
200
250
300
VCC = 5.0V
fS
Clock Frequency MHz
ICC(f)
Supply
Current
mA
fdata = 1/2 fS
TA = 25oC
CL = 0 pF
VCC = 4.5V
VCC = 5.5V
5611 drw02a
80
90
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723656/723666/723676 with CLKA,
CLKB and CLKC set to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs
driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
PT = VCC x [ICC(f) + (N x
ICC x dc)] + Σ(CL x VCC2 X fo)
N
where:
N
=
number of inputs driven by TTL levels
ICC =
increase in power supply current for each input at a TTL HIGH level
dc
=
duty cycle of inputs at a TTL HIGH level of 3.4V
CL
=
outputcapacitanceload
fo
=
switching frequency of an output
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