15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
JANUARY 13, 2009
Figure 12. Read Programmable Registers (IDT Standard Mode)
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
NOTES:
1. n =
PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4.
PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting (
FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
WCLK
tCLKH
tCLKL
tCLK
tENS
tENH
LD
WEN
D0-D15
tDS
tDH
PAE OFFSET
PAF OFFSET
D0-D11
PAE OFFSET
tENS
3139 drw 11
RCLK
tCLKH
tCLKL
tCLK
tENS
tENH
LD
REN
Q0-Q15
PAE OFFSET
PAF OFFSET
PAE OFFSET
UNKNOWN
tA
tENS
3139 drw 12
WCLK
tCLKH
tCLKL
tENS
tENH
WEN
PAE
tENS
tPAEA
n + 1 words in FIFO(2),
n+2wordsinFIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
RCLK
tPAEA
REN
3139 drw 13
n words in FIFO(2),
n + 1 words in FIFO(3)
Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes)