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參數(shù)資料
| 型號： | IDT72T51253L6BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| 中文描述： | 128K X 18 OTHER FIFO, 3.7 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 45/55頁 |
| 文件大?。?/td> | 544K |
| 代理商： | IDT72T51253L6BBI |
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45
IDT72T51233/72T51243/72T51253 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
OE
*G*
W
D - M + 2
D0 Q1
t
A
*I*
t
A
W
0
D6 Q2
*F*
t
QH
t
QS
D0 Q1
111 xx
Device 7
110 10
*D*
*E*
t
AH
t
AS
t
STH
t
STS
D6Q2
W
D-M+1
t
A
W
X +1
Prev. Q
t
OLZ
REN
RADEN
ESTR
WRADD
t
AH
000 01
t
AS
RDADD
D0Q1
*A*
*B*
000 xx
t
QH
t
QS
t
STH
t
STS
6115 drw29
xxxxxx0x
Device 0
*BB*
*CC*
*DD*
*EE*
*FF*
t
PAFLZ
Device 0
Device 0
t
PAF
t
PAF
xxxxxx0x
Device 0
Device 0
Device 0
t
PAFHZ
HIGH-Z
HIGH-Z
t
PAFLZ
t
WAF
*AA*
Device 0
PAF
n
Bus
PAF
n
D
X
Quad y
Prev.
PAF
n
D
X
Quad y
Device 0
PAF
Qout
W
X
Prev. Q
Device 0
FSTR
t
A
WCLK
t
SKEW3
2
3
D0 Q1
WEN
t
ENS
t
ENH
WADEN
t
QH
t
QS
t
AH
t
AS
t
AH
t
AS
Din
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Word W
y
D0 Q1
W
y+1
D0 Q1
W
y+2
D0 Q1
*C*
t
AH
t
AS
*H*
1
HIGH - Z
*GG*
Figure 25.
PAF
n - Direct Mode, Flag Operation
Cycle:
*A*
Q1 of device 0 is selected for read operations.
The last word in the output register is available on Qout.
OE
was previously taken LOW so the output bus is in Low-Impedance.
*AA*
Device 0 is selected for the
PAF
n bus. The bus is currently providing status of a previously selected quadrant, Quad Y of device X.
*B*
No read operation.
*BB*
Queue 1 of device 0 is selected on the write port.
*C*
Word, Wx+1 is read out fromthe previous queue due to the FWFT effect.
*CC*
The
PAF
n bus is updated with the quadrant selected on the previous cycle, Device 0
PAF
[1] is LOW showing the status of queue 1.
The
PAF
n outputs of the device previously selected on the
PAF
n bus go to High-Impedance.
*D*
Device 7 is selected for the
PAF
n bus.
Word, Wd-m+1 is read fromQ1 D0 due to the FWFT operation. This read is at the
PAF
n boundary of queue D0 Q1. This read will cause the
PAF
[1] output to go from
LOW to HIGH (almost full to not almost full), after a delay t
SKEW3
+ WCLK + tPAF. If t
SKEW3
is violated add an extra WCLK cycle.
*DD*
No write operation.
*E*
No read operations occur,
REN
is HIGH.
*EE*
PAF
[1] goes HIGH to show that D0 Q1 is not almost empty due to the read on cycle *C*
The active queue
PAF
flag of device 0 goes fromHigh-Impedance to Low-Impedance.
Word, Wy is written into D0 Q1.
*F*
Queue 2 of Device 6 is selected for read operations.
*FF*
Word, Wy+1 is written into D0 Q1.
*G*
Word, Wd-m+2 is read out due to FWFT operation.
*GG*
PAF
[1] and the discrete
PAF
flag go LOW to show the write on cycle *DD*causes Q1 of D0 to again go almost full.
Word, Wy+2 is written into D0 Q1.
*H*
No read operation.
*I*
Word, W0 is read fromQ6 of D2, selected on cycle *F* due to FWFT.
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| IDT72T51253L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51253L6BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233 | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L5BB | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
| IDT72T51233L5BBI | 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 bits and 2,359,296 bits |
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